w83195bg-202 Winbond Electronics Corp America, w83195bg-202 Datasheet - Page 16

• Manufacturer Part Number: w83195bg-202
• Description: Clock For Via Chipsets
• Manufacturer: Winbond Electronics Corp America

Table-2 CPU divider ratio selection Table
7.14 Register 13: Step-less Enable Control (Default: 3Fh)
7.15 Register 14: Control (Default: 10h)
BIT
BIT
7
6
7
6
5
4
3
2
1
0
0
Bit2
MSB
DRI_CONT
Reserved
EN_MN_PROG
LSB
NAME
Reserved
Reserved
IVAL<3>
IVAL<2>
IVAL<1>
IVAL<0>
KVAL0
N<10>
NAME
CLOCK GEN. FOR AMD K8 SYSTEM SERIES CHIPSET
PWD
0
0
0
1
X
CPUT / PCIE_T output state in during POWER DOWN assertion.
1: Driven (2*Iref), 0: Tristate (Floating)
CPUT / PCIE_T output state in during STOP Mode assertion.
1: Driven (6*Iref), 0: Tristate (Floating)
Complementary parts always tri-state (floating) in power down or
stop mode.
Reserved
PWD
0
0
1
1
1
1
1
1
0: Output frequency depend on frequency table
1: Program all clock frequency by changing M/N value
The equation is
Once the watchdog timer timeout, the bit will be clear.
Then the frequency will be decided by hardware default
FS<4:0> or desired
[4:0] depend on EN_SAFE_FREQ (Reg0 - bit 0).
Programmable N divisor bit 10.
Reserved
Reserved
Charge pump current
VCO =14.318MHz*(N+4)/ M.
Div2
Div8
00
W83195BR-202/W83195BG-202
- 12 -
DESCRIPTION
Div3
Div8
01
DESCRIPTION
frequency select SAF_FREQ
Bit1, 0
CPU
Div4
Div8
10
Div6
Div8
11
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TYPE
R/W
R/W
R/W