cy7b9940v Cypress Semiconductor Corporation., cy7b9940v Datasheet - Page 6

• Manufacturer Part Number: cy7b9940v
• Description: High Speed Multifrequency Pll Clock Buffer
• Manufacturer: Cypress Semiconductor Corporation.

Electrical Characteristics
Capacitance
Switching Characteristics
Over the Operating Range
Document Number: 38-07271 Rev. *C
Operating Current
I
I
C
f
f
t
t
t
t
t
t
t
t
t
t
t
Notes
Parameter
CCI
CCN
in
out
SKEWPR
SKEWBNK
SKEW0
SKEW1
CCJ1-3
CCJ4-12
PD
PDDELTA
REFpwh
REFpwl
r
5. I
6. This is dependent upon frequency and number of outputs of a bank being loaded. The value indicates maximum I
7. This is for non-three level inputs.
8. Assumes 25 pF Max. Load Capacitance up to 185 Mhz. At 200 MHz the max load is 10 pF.
9. Both outputs of pair must be terminated, even if only one is being used.
10. Each package must be properly decoupled.
11. AC parameters are measured at 1.5V, unless otherwise indicated.
12. Test Load C
13. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when all outputs
14. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
15. Tested initially and after any design or process changes that may affect these parameters.
16. Rise and fall times are measured between 2.0V and 0.8V.
Parameter
Parameter
/t
IN
f
and all other clock output banks to run at half the maximum frequency. FS and OUTPUT_MODE are asserted to the HIGH state.
25 pF terminated to 50Ω at V
are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF.
CCI
measurement is performed with Bank1 and FB Bank configured to run at maximum frequency (f
L
Clock input frequency
Clock input frequency
Matched pair skew
Intrabank skew
Output-Output skew (same frequency and phase, rise to rise, fall
to fall)
Output-Output skew (same frequency and phase, other banks at
different frequency, rise to rise, fall to fall)
Cycle-to-cycle jitter (divide by 1 output frequency,
FB = divide by 1, 2, 3)
Cycle-to-cycle jitter (divide by 1 output frequency,
FB = divide by 4, 5, 6, 8, 10, 12)
Propagation delay, REF to FB Rise
Propagation delay difference between two devices
REF input (pulse width HIGH)
REF input (pulse width LOW)
Output rise/fall time
= 25 pF, terminated to V
Internal operating
current
Output current
dissipation/pair
Input capacitance
Description
Description
[12, 13]
[7, 8, 9, 10, 11]
CC
/2.
[12, 13]
[6]
[12, 13]
CC
[16]
/2 with 50Ω.
Over the Operating Range (continued)
CY7B9930V
CY7B9940V
CY7B9930V
CY7B9940V
T
A
Description
= 25
[15]
[15]
°
C, f = 1 MHz, V
[12, 13]
Test Conditions
CC
[14]
= 3.3V
CY7B9930V
CY7B9940V
CY7B9930V
CY7B9940V
R
LOAD
V
Test Conditions
CC
C
V
LOAD
= Max., f
CC
= 50Ω at V
f
MAX
= Max.,
NOM
= 25 pF,
CY7B9930/40V-2 CY7B9930/40V-5
–250
Min.
0.15
2.0
2.0
12
24
12
24
= 100 MHz for CY7B9930V, f
–
–
–
–
–
–
–
MAX
CC
[5]
/2,
CY7B9930V, CY7B9940V
Max.
CCN
100
200
100
200
185
200
250
250
150
100
250
200
2.0
–
–
RoboClockII™ Junior,
at maximum frequency and maximum load of
Min.
Min.
–
–
–
–
–
–500
Min.
0.15
2.0
2.0
12
24
12
24
–
–
–
–
–
–
NOM
= 200 MHz for CY7B9940V),
Max.
Max.
200
200
40
50
Max.
5
100
200
100
200
185
250
550
650
150
100
500
200
2.0
–
–
Page 6 of 11
ps Peak-
ps Peak-
Unit
Peak
Peak
Unit
MHz
MHz
MHz
MHz
Unit
mA
mA
mA
mA
pF
ps
ps
ps
ps
ps
ps
ns
ns
ns
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