cy7b995ait Cypress Semiconductor Corporation., cy7b995ait Datasheet - Page 3

• Manufacturer Part Number: cy7b995ait
• Description: 2.5/3.3v 200-mhz High-speed Multi-phase Pll Clock Buffer
• Manufacturer: Cypress Semiconductor Corporation.

Table 1. Pin Definitions - 44 Pin TQFP Package
Device Configuration
The outputs of the CY7B995 can be configured to run at
frequencies ranging from 6 MHz to 200 MHz. The feedback input
divider is controlled by the 3-level DS[0:1] pins as indicated in
Table 3
by the 3-level PD#/DIV pin as indicated in
Document #: 38-07337 Rev. *D
39
17
37
2
4
34, 33, 36, 35,
43, 42, 1, 44
41
26,27,20,21,
13,14,7,8
32, 31
3
30
5,6
15,16
19,28,29
18,40
9-12, 22-25, 38 V
Notes
1. PD indicates an internal pull down and ‘PU’ indicates an internal pull up.
2. A bypass capacitor (0.1μF) must be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins, their high
3. When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections
4. When PD#/DIV = LOW, the device enters power down mode.
frequency filtering characteristic is cancelled by the lead inductance of the traces.
remain in effect unless nF[1:0] = LL.
Pin
on page 4, and the reference input divider is controlled
REF
FB
TEST
sOE#
PE/HD
nF[1:0]
FS
nQ[1:0]
DS[1:0]
PD#/DIV
LOCK
V
V
V
V
DD
DD
DD
SS
Name
DD
Q3
Q1
[2]
Q4
[2]
[2]
[2]
PWR Power
PWR Power
PWR Power
PWR Power
PWR Power
I, PD LVTTL
I, PU 3-Level
I, PU 3-Level
IO
O
O
I
I
I
I
I
I
[1]
LVTTL/LVCMOS
3-Level
LVTTL
LVTTL
3-Level
3-Level
3-Level
LVTTL
Type
Table
2.
Reference Clock Input.
Feedback Input.
When MID or HIGH, disables PLL
for normal operation.
Synchronous Output Enable. When HIGH, it stops clock outputs
(except 2Q0 and 2Q1) in a LOW state (for PE/HD = H or M) – 2Q0, and
2Q1 may be used as the feedback signal to maintain phase lock. When
TEST is held at MID level and sOE# is HIGH, the nF[1:0] pins act as output
disable controls for individual banks when nF[1:0] = LL. Set sOE# LOW
for normal operation.
Selects Positive or Negative Edge Control, and High or Low output
Drive Strength. When LOW/HIGH, the outputs are synchronized with the
negative/positive edge of the reference clock respectively. When at MID
level, the output drive strength is increased and the outputs synchronize
with the positive edge of the reference clock. See
Selects Frequency and Phase of the Outputs. See
Table
Selects VCO Operating Frequency Range. See
Four banks of two outputs. See
settings.
Selects Feedback Divider. See
Power down and Reference Divider Control. When LOW, shuts off
entire chip. When at MID level, enables the reference divider. See
for settings.
PLL Lock Indication Signal. HIGH indicates lock, LOW indicates the
PLL is not locked, and outputs may not be synchronized to the input.
Power supply for Bank 4 Output Buffers. See
supply level constraints.
Power supply for Bank 3 Output Buffers. See
supply level constraints.
Power supply for Bank 1 and Bank 2 Output Buffers. See
page 5 for supply level constraints.
Power supply for the Internal Circuitry. See
supply level constraints.
Ground
6,
Table
Table 2. Reference Divider Settings
8, and
PD#/DIV
Table 9
L
M
H
[4]
on page 4.
Description
Table 3
Table 6
[3]
. REF goes to all outputs. Set LOW
RoboClock
on page 4.
on page 4 for frequency
R–Reference Divider
Table 11
Table 11
Table 11
Table 10
Table 7
N/A
Table
1
2
on page 5 for
®
on page 5 for
on page 5 for
on page 4.
on page 5.
, CY7B995
4,
Table 11
Table
Table 2
Page 3 of 13
5,
on
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