cy7b995ait Cypress Semiconductor Corporation., cy7b995ait Datasheet - Page 4

• Manufacturer Part Number: cy7b995ait
• Description: 2.5/3.3v 200-mhz High-speed Multi-phase Pll Clock Buffer
• Manufacturer: Cypress Semiconductor Corporation.

Table 3. Feedback Divider Settings
In addition to the reference and feedback dividers, the CY7B995
includes output dividers on Bank3 and Bank4, which are
controlled by 3F[1:0] and 4F[1:0] as indicated in
Table
Table 4. Output Divider Settings – Bank 3
Table 5. Output Divider Settings – Bank 4
The divider settings and the FB input to any output connection
needed to produce various output frequencies are summarized
in
Table 6. Output Frequency Settings.
Document #: 38-07337 Rev. *D
1Qn or 2Qn
3Qn
DS[1:0] N-Feedback Input
Notes
Configuration
5. These states are used to program the phase of the respective banks. See
6. These outputs are undivided copies of the VCO clock. The formulas in this column can be used to calculate the VCO operating frequency (FNOM) at a given
Table
Connected to
MM
MH
HM
LM
ML
HH
LH
HL
LL
reference frequency (FREF), and divider and feedback configuration. The user must select a configuration and a reference frequency that generates a VCO
frequency, and is within the range specified by FS pin. See
FB Input
5, respectively.
Other
Other
3F[1:0]
4F[1:0]
6.
HH
LL
LL
[5]
[5]
Divider
(N / R) x F
(N / R) x K x
F
10
12
1Q[0:1] and
REF
2
3
4
5
1
6
8
2Q[0:1]
[6]
K - Bank3 Output Divider
REF
M- Bank4 Output Divider
Output Frequency
(N / R) x (1 /
K) x F
(N / R) x F
Permitted Output Divider
3Q[0:1]
Connected to FB
REF
2
4
1
2
1
1,2 or 4
1,2 or 4
REF
1 or 2
1 or 2
1 or 2
1 or 2
1
1
1
(N / R) x (1 /
M) x F
(N / R) x (K /
M) x F
Table
4Q[0:1]
Table 4
REF
REF
7.
and
Table 8
The 3-level FS control pin setting determines the nominal
operating frequency range of the divide-by-one outputs of the
device. The CY7B995 PLL operating frequency range that corre-
sponds to each FS level is given in
Table 7. Frequency Range Select
Selectable output skew is in discrete increments of time units
(t
maximum nominal frequency. The equation used to determine
the t
where MF is a multiplication factor which is determined by the FS
setting as indicated in
Table 8. MF Calculation
Table 9. Output Skew Settings
and
4Qn
nF[1:0]
Configuration
U
Connected to
LL
).The value of t
MM
MH
HM
LM
ML
HH
LH
HL
Table
FS
M
H
U
L
FB Input
[7]
value is: t
9.
FS
M
H
L
(1Q[0:1],2Q[0:1])
MF
32
16
Zero Skew
8
U
Skew
+1t
+2t
+3t
+4t
–4t
–3t
–2t
–1t
= 1 / (f
(N / R) x M x
F
U
1Q[0:1] and
REF
2Q[0:1]
U
U
U
U
U
U
U
U
is determined by the FS setting and the
Table
f
NOM
NOM
RoboClock
[6]
8.
x MF)
PLL Frequency Range
at which t
Output Frequency
Divide By 2
Divide By 4
(N / R) x (M /
K) x F
Zero Skew
(3Q[0:1])
48 to 100 MHz
96 to 200 MHz
24 to 50 MHz
Skew
Table
–6t
–4t
–2t
+2t
+4t
+6t
3Q[0:1]
31.25
62.5
REF
125
U
U
U
U
U
U
U
7.
is 1.0 ns (MHz)
®
, CY7B995
(N / R) x F
Divide By 2
Zero Skew
Inverted
(4Q[0:1])
4Q[0:1]
Skew
Page 4 of 13
–6t
–4t
–2t
+2t
+4t
+6t
U
U
U
U
U
U
[8]
REF
[+] Feedback
[+] Feedback