lmk02002 National Semiconductor Corporation, lmk02002 Datasheet - Page 11

• Manufacturer Part Number: lmk02002
• Description: Precision Clock Conditioner With Integrated Pll
• Manufacturer: National Semiconductor Corporation

2.3.5 CLKoutX_EN bit -- Clock Output Enables
These bits control whether an individual clock output is en-
abled or not. If the EN_CLKout_Global bit (See 2.5.4) is set
to zero or if GOE pin is held low, all CLKoutX_EN bit states
will be ignored and all clock outputs will be disabled. See 1.8
for more information on CLKout states.
2.4 REGISTER R11
This register only has one bit and only needs to be pro-
grammed in the case that the phase detector frequency is
greater than 20 MHz and digital lock detect is used. Other-
wise, it is automatically defaulted to the correct values.
2.4.1 DIV4
This bit divides the frequency presented to the digital lock de-
tect circuitry by 4. It is necessary to get a reliable output from
the digital lock detect output in the case of a phase detector
frequency greater than 20 MHz.
2.5 REGISTER R14
The LMK02002 requires register R14 to be programmed as
shown in the register map (see 2.2).
2.5.1 PLL_R[11:0] -- R Divider Value
These bits program the PLL R Divider and are programmed
in binary fashion.
2.5.2 PLL_MUX[3:0] -- Multiplexer Control for LD Pin
These bits set the output mode of the LD pin. The table below
lists several different modes.
CLKoutX_EN bit
0
0
0
0
1
.
.
CLKoutX_DLY[3:0]
0
0
0
0
1
.
.
DIV4
0
0
0
0
1
0
1
0
1
.
.
0
0
0
0
1
.
.
10
11
12
13
14
15
9
PLL_R[11:0]
0
0
0
0
1
.
.
Divided by 4; Phase detector frequency
Not divided; Phase detector frequency
GOE pin = High / No
0
0
0
0
1
EN_CLKout_Global
Digital Lock Detect Circuitry Mode
.
.
0
0
0
0
1
.
.
Conditions
Connect 1
bit = 1
0
0
0
0
1
.
.
≤
20 MHz (default)
0
0
0
1
1
.
.
> 20 MHz
0
0
0
0
1
.
.
0
0
1
1
1
.
.
Delay (ps)
Disabled (default)
1350
1500
1650
1800
1950
2100
2250
0
1
0
0
1
CLKoutX State
.
.
PLL R Divide
Enabled
10 (default)
Invalid
Value
4095
...
...
1
2
11
2.5.3 POWERDOWN bit -- Device Power Down
This bit can power down the device. Enabling this bit powers
down the entire device and all blocks, regardless of the state
of any of the other bits or pins.
2.5.4 EN_CLKout_Global bit -- Global Clock Output
Enable
This bit overrides the individual CLKoutX_EN bits (See 2.3.5).
When this bit is set to 0, all clock outputs are disabled, re-
gardless of the state of any of the other bits or pins. See 1.8
for more information on CLKout states.
2.5.5 PLL_CP_TRI bit -- PLL Charge Pump TRI-STATE
This bit sets the PLL charge pump TRI-STATE.
2.5.6 PLL_CP_POL bit -- PLL Charge Pump Polarity
This bit sets the polarity of the charge pump to either negative
or positive. A negative charge pump is used with a VCO or
VCXO which decreases frequency with increasing tuning volt-
age. A positive charge pump is used with a VCO or VCXO
which increases frequency with increasing tuning voltage.
PLL_MUX[3:0]
EN_CLKout_Global
POWERDOWN bit
12 to 15
PLL_CP_POL
PLL_CP_TRI
10
11
0
1
2
3
4
5
6
7
8
9
bit
0
1
0
1
0
1
0
1
Open Drain NMOS
Open Drain PMOS
Output Type
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Entire Device Powered Down
Hi-Z
PLL Charge Pump Polarity
Normal Operation (default)
Normal Operation (default)
Normal operation (default)
PLL Charge Pump
Negative (default)
Clock Outputs
TRI-STATE
Invalid
Invalid
Invalid
Positive
All Off
Mode
Digital Lock Detect
Digital Lock Detect
N Divider Output/2
R Divider Output/2
Disabled (default)
(50% Duty Cycle)
(50% Duty Cycle)
LD Pin Function
(Active High)
(Active Low)
Analog Lock
Analog Lock
Analog Lock
Logic High
Logic Low
Detect
Detect
Detect
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