lmk02002 National Semiconductor Corporation, lmk02002 Datasheet - Page 5

• Manufacturer Part Number: lmk02002
• Description: Precision Clock Conditioner With Integrated Pll
• Manufacturer: National Semiconductor Corporation

V
V
I
I
t
t
t
t
t
t
t
IH
IL
CS
CH
CWH
CWL
ES
CES
EWH
IH
IL
Note 4: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 5: See 3.4 for more current consumption / power dissipation calculation information.
Note 6: For all frequencies the slew rate, SLEW
Note 7: A specification in modeling PLL in-band phase noise is the 1/f flicker noise, L
dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = L
(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure L
slope close to the carrier. A high phase detector frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). L
(f) can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL inband phase noise performance is the sum of
L
Note 8: A specification in modeling PLL in-band phase noise is the Normalized Phase Noise Contribution, L
L
detector frequency of the synthesizer. L
smaller then the loop bandwidth of the PLL, and yet large enough to avoid a substantial noise contribution from the reference and flicker noise. L
masked by the reference oscillator performance if a low power or noisy source is used.
Note 9: The Clock Distribution Section includes all parts of the device except the PLL section. Typical Additive Jitter specifications apply to the clock distribution
section only.
Note 10: Specification is guaranteed by characterization and is not tested in production.
Note 11: Applies to GOE, LD, and SYNC*.
Note 12: Applies to CLKuWire, DATAuWire, and LEuWire.
Serial Data Timing Diagram
Data bits set on the DATAuWire signal are clocked into a shift register, MSB first, on each rising edge of the CLKuWire signal. On
the rising edge of the LEuWire signal, the data is sent from the shift register to the addressed register determined by the LSB bits.
After the programming is complete the CLKuWire, DATAuWire, and LEuWire signals should be returned to a low state.
Symbol
PLL_flicker
PLL_flat
(f) – 20log(N) – 10log(f
(f) and L
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
Low-Level Input Current
Data to Clock Set Up Time
Data to Clock Hold Time
Clock Pulse Width High
Clock Pulse Width Low
Clock to Enable Set Up Time
Enable to Clock Set Up Time
Enable Pulse Width High
PLL_flat
(f).
COMP
). L
Parameter
PLL_flat
PLL_flat
(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz Bandwidth and f
(f) contributes to the total noise, L(f). To measure L
Fin
, is measured between 20% and 80%.
Digital MICROWIRE Interfaces (Note 12)
MICROWIRE Timing
V
V
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
IH
IL
= 0
= Vcc
5
PLL_flicker
Conditions
(f), which is dominant close to the carrier. Flicker noise has a 10
PLL_flat
(f) the offset frequency, f, must be chosen sufficiently
PLL_flicker
PLL_flat
PLL_flicker
(10 kHz) - 20log(Fout / 1 GHz), where L
(f), of the PLL and is defined as PN1Hz =
(f) it is important to be on the 10 dB/decade
Min
-5.0
-5.0
1.6
25
25
25
25
25
25
8
Typ
COMP
Max
Vcc
0.4
5.0
5.0
PLL_flat
www.national.com
is the phase
30023303
(f) can be
PLL_flicker
PLL_flicker
Units
µA
µA
ns
ns
ns
ns
ns
ns
ns
V
V