mk2069-03 Integrated Device Technology, mk2069-03 Datasheet

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mk2069-03

Manufacturer Part Number
mk2069-03
Description
Vcxo-based Clock Translator With High Multiplication
Manufacturer
Integrated Device Technology
Datasheet
VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION MK2069-03
Description
The MK2069-03 is a VCXO (Voltage Controlled Crystal
Oscillator) based clock generator that offers system
synchronization, jitter attenuation and frequency
translation. It can accept an input clock over a wide range of
frequencies and produces a de-jittered, low phase noise
clock output. The device is optimized for user configuration
by providing access to all major PLL divider functions. No
power-up programming is needed as configuration is pin
selected. External VCXO loop filter components provide an
additional level of performance tailoring.
The MK2069-03 features a very wide range VCXO PLL
feedback divider, allowing high frequency multiplication
ratios and therefore the input of very low input reference
frequencies. The lock detector (LD) output serves as a
clock status monitor. The clear (CLR) input enables rapid
synchronization to the phase of a newly selected input
clock, while eliminating the generation of extra clock cycles
and wander caused by memory in the PLL feedback divider.
CLR also serves as a temporary holdover function when
kept low.
Block Diagram
IDT™ / ICS™ VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION 1
IC L K
C L R
IS E T
V C X O
P L L
D etector
P hase
L F
L F R
C harge
P um p
F V D iv id e r
1 to 4 0 9 6
X 1
F V 1 1 :0
P u lla b le
V C X O
x ta l
12
X 2
F P V D iv id e r
F P V 5 :0
2 to 6 5
1 ,2 ,4 ,6 ,8 ,
1 0 ,1 2 ,1 6
D iv id e r
S V 2 :0
S V
6
3
L o c k D e te c to r
L D C
D iv id e r
R T 1 :0
1 to 4
Features
R T
Wide range VCXO PLL feedback divider allows high
frequency multiplication ratios and the input of very low
input reference frequencies
Input clock frequency of <1kHz to 13.5MHz
Output clock frequency of 500kHz to 160MHz
PLL lock status output
VCXO-based clock generation offers very low jitter and
phase noise generation, even with low frequency or jittery
input clock.
PLL Clear function (CLR input) allows the VCXO to
free-run, offering a short term holdover function.
2nd PLL provides frequency translation of VCXO PLL to
higher or alternate output frequencies.
Device will free-run in the absence of an input clock (or
stopped input clock) based on the VCXO frequency
pulled to minimum frequency limit.
Low power CMOS technology
56 pin TSSOP package
Single 3.3V power supply
2
T ra n s la to r
P L L
L D R
F T D iv id e r
1 to 6 4
F T 5 :0
V C O
6
D iv id e r
2 ,4 ,8 ,1 6
S T 1 :0
S T
MK2069-03
2
DATASHEET
G N D
V D D
4
4
REV J 030906
V C L K
O E V
T C L K
O E T
R C L K
O E R
L D
O E L

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mk2069-03 Summary of contents

Page 1

... External VCXO loop filter components provide an additional level of performance tailoring. The MK2069-03 features a very wide range VCXO PLL feedback divider, allowing high frequency multiplication ratios and therefore the input of very low input reference frequencies. The lock detector (LD) output serves as a clock status monitor ...

Page 2

... SV Divider Ratio Divider Ratio Divider Ratio Notes 2 For FT addresses Divide = Address + Divider Ratio MK2069-03 REV J 030906 ...

Page 3

... Ground Ground connection for internal digital circuitry. Power Lock detector threshold setting circuit connection. Refer to circuit on page 10. Output VCXO PLL Reference Clock output. Ground Ground connection for output drivers (VCLK, TCLK, RCLK, LD, LDR). VCXO AND SYNTHESIZER Pin Description MK2069-03 REV J 030906 ...

Page 4

... SV1 56 SV2 Functional Description The MK2069- PLL (Phase Locked Loop) based clock generator that generates output clocks synchronized to an input reference clock. It contains two cascaded PLL’s with user selectable divider ratios. The first PLL is VCXO-based and uses an external pullable crystal as part of the normal “ ...

Page 5

... IDT™ / ICS™ VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION 5 VCXO AND SYNTHESIZER Application Information The MK2069- mixed analog / digital integrated circuit that is sensitive to PCB (printed circuit board) layout and external component selection. Used properly, the device will provide the same high performance expected from a canned VCXO-based hybrid timing device, but at a lower cost ...

Page 6

... MK2069-03 Loop Response and JItter Attenuation Characteristics The MK2069-03 will reduce the transfer of phase jitter existing on the input reference clock to the output clock. This operation is known as jitter attenuation. The low-pass frequency response of the VCXO PLL loop is the mechanism that provides input jitter attenuation ...

Page 7

... C P and C in the loop S P VCXO AND SYNTHESIZER C S ----- - = P 20 value that would be used for a damping factor S value that is too low use the filter P should be increased in value until it P MK2069- too P REV J 030906 ...

Page 8

... SET VCXO Gain ( increases CP VCXO AND SYNTHESIZER 10E+6 Recommended Range of Operation ) vs. XTAL Frequency MK2069-03 REV J 030906 3 0 ...

Page 9

... By using CLR in this fashion VCLK will align to the input clock phase with only one or two VCLK cycle slips resulting. VCXO AND SYNTHESIZER C Loop Loop Passband P BW Damp. Peaking (-3dB) 4.0 0.15dB at 1Hz 1.4 1.2dB at 6Hz 4.5 0.12dB at 1Hz . It is useful when S MK2069-03 Note REV J 030906 ...

Page 10

... RLD and CLD components but the LD output will not be used, RLD can remain unstuffed and CLD can be replaced with a resistor (< 10 kohm). Power Supply Considerations As with any integrated clock device, the MK2069-03 has a special set of power supply requirements: • The feed from the system power supply must be filtered for noise that can cause output clock jitter ...

Page 11

... The MK2069-03 incorporates variable load capacitors on-chip which “pull” or change the frequency of the crystal. The crystals specified for use with the MK2069-03 are designed to have zero frequency error when the total of on-chip + stray capacitance is 14pF. To achieve this, the layout should use short traces between the MK2069-03 and the crystal ...

Page 12

... In applications that are especially sensitive to noise, such as SONET or G-Bit ethernet transceivers, some or all of the following crystal shielding techniques should be considered. This is especially important when the MK2069-03 is placed near high speed logic or signal traces. The following techniques are illustrated on the Recommended PCB Layout drawing. ...

Page 13

... The crystal should be keep away from these clock sources. The IDT Applications Note MAN05 may also be referenced for additional suggestions on layout of the crystal section. IDT™ / ICS™ VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION 13 VCXO AND SYNTHESIZER MK2069-03 REV J 030906 ...

Page 14

... CBD G A CBB G 603 603 603 43 MK2069 603 40 39 RLD G 38 603 37 CLD 36 603 (film type current value 33 omitted. See text on page 10. MK2069-03 G REV J 030906 ...

Page 15

... LDR pin. Use RCLK as the scope trigger. LDR will produce a negative pulse equal in length to the charge pump pulse. 3.5) Filter leakage can also be caused by the use of improper loop capacitors. Refer to the section titled ‘Loop Filter Capacitor Type’ on page 9. /20 MK2069-03 REV J 030906 ...

Page 16

... VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK2069-03. These ratings, which are standard values for IDT industrial rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied ...

Page 17

... max prior to the application of VDD, providing utility in hot-plug line card IH VCXO AND SYNTHESIZER Min. Typ. Max. Units 3.15 3.3 3. VDD + V 0.4 -0.4 0.8 V 200 k VDD/2+1 VDD + V 0.4 VDD/2+1 5.5 V -0.4 VDD/2-1 V -10 +10 A -10 + VDD-0.4 V 2.4 V 0.4 V ±50 mA ± VDD V MK2069-03 REV J 030906 ...

Page 18

... 2.0 to 0.8V, C =15pF OF L VCXO AND SYNTHESIZER Min. Typ. Max. Units 13.5 27 MHz ±115 ±150 ppm -300 -150 ppm 0.001 27 MHz 10 nsec 0 320 MHz 105 2.5 160 MHz 0.5 VCLK Period 1 1 MK2069-03 REV J 030906 ...

Page 19

... IDT™ / ICS™ VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION 19 Symbol Conditions t 0.8 to 2.0V, C =15pF 2.0 to 0.8V, C =15pF Rising edges, C =15pF Rising edges, C =15pF Rising edges, C =15pF OUT VCXO AND SYNTHESIZER Min. Typ. Max. Units 0. 0. 2 1.5 + MK2069-03 REV J 030906 ...

Page 20

... MK2069-03GI MK2069-03GITR MK2069-03GI While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied ...

Page 21

... MK2069-03 VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc ...

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