mk2069-03 Integrated Device Technology, mk2069-03 Datasheet - Page 9

• Manufacturer Part Number: mk2069-03
• Description: Vcxo-based Clock Translator With High Multiplication
• Manufacturer: Integrated Device Technology

Example Loop Filter Component Value
Loop Filter Capacitor Type
Loop filters must use specific types of capacitors.
Recommendations for these capacitors can be found at
www.idt.com.
Input Phase Compensation Circuit
The VCXO PLL includes a special input clock phase
compensation circuit. It is used when changing the phase of
the input clock, which might occur when selecting a new
reference input through the use of an external clock
multiplexer.
The phase compensation circuit allows the VCXO PLL to
quickly lock to the new input clock phase without producing
extra clock cycles or clock wander, assuming the new clock
is at the same frequency.
Input pin CLR controls the phase compensation circuit. CLR
must remain high for normal operation. When used in
conjunction with an external multiplexer (MUX), CLR should
be brought low prior to MUX reselection, then returned high
after MUX reselection. This prevents the VCXO PLL from
attempting to lock to the new input clock phase associated
with the input clock.
IDT™ / ICS™ VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION 9
Frequency
Detector
MK2069-03
VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION
Phase
8 kHz
8 kHz
8 kHz
Notes:
1) This filter configuration assures a passband ripple compliant with Bellcore GR-1244-CORE to satisfy wander
transfer requirements (<0.2 dB ripple is required) of a network node. It can be used following a system synchronizer
such as the MT9045 to provide clock jitter attenuation while maintaining Stratum 3 compliance. A 155.52 MHz TCLK
output generated with the VCXO PLL configuration will be OC-3 and OC-12 timing jitter compliant.
2) This is a reduced cost and size variant of the above filter, due to the decreased size of C
GR-1244-CORE compliance is not needed.
3) This configuration is used to generate a DS3 clock of 44.736 MHz at the TCLK output. This configuration is
GR-1244-CORE compliant when used following a system synchronizer.
22.368
(MHz)
19.44
19.44
Freq
Xtal
Div
SV
1
1
1
22.368
VCLK
(MHz)
19.44
19.44
FV Div x
FPV Div
2430
2430
2796
R
1 M
1 M
1 M
SET
560 k
560 k
680 k
R
S
0.1 F 4.7 nF 27 Hz
When CLR is high, the VCXO PLL operates normally.
When CLR is low, the VCXO PLL charge pump output is
inactivated which means that no charge pump correction
pulses are provided to the loop filter. During this time, the
VCXO frequency is held constant by the residual charge or
voltage on the PLL loop filter, regardless of the input clock
condition. However, the VCXO frequency will drift over time,
eventually to the minimum pull range of the crystal, due to
leak-off of the loop filter charge. This means that CLR can
provide a holdover function, but only for a very short
duration, typically in milliseconds.
Upon bringing CLR high, the FV divider is reset and begins
counting with the first positive edge of the new input clock,
and the charge pump is re-activated (FPV is not reset). By
resetting the FV Divider, the memory of the previous input
clock phase is removed from this feedback divider,
eliminating the generation of extra VCLK clock cycles that
would occur if the loop was to re-lock under normal means.
Lock time is also reduced, as is the generation of clock
wander.
By using CLR in this fashion VCLK will align to the input
clock phase with only one or two VCLK cycle slips resulting.
1 F
1 F
C
S
4.7 nF 22 Hz
4.7 nF 20 Hz
C
P
(-3dB)
Loop
BW
Damp.
Loop
4.0
1.4
4.5
0.15dB at 1Hz
0.12dB at 1Hz
1.2dB at 6Hz
Passband
Peaking
VCXO AND SYNTHESIZER
S
. It is useful when
MK2069-03
Note
1
2
3
REV J 030906