mk2069-03 Integrated Device Technology, mk2069-03 Datasheet - Page 10

• Manufacturer Part Number: mk2069-03
• Description: Vcxo-based Clock Translator With High Multiplication
• Manufacturer: Integrated Device Technology

When CLR is not used, the number of VCLK cycle slips can
be as high the FV Divider value.
TCLK is always locked to VCLK regardless of the state of
the CLR input.
Lock Detection
The MK2069-03 includes a lock detection feature that
indicates lock status of VCLK relative to the selected input
reference clock. When phase lock is achieved (such as
following power-up), the LD output goes high. When phase
lock is lost (such as when the input clock stops, drifts beyond
the pullable range of the crystal, or suddenly shifts in
phase), the LD output goes low.
The definition of a “locked” condition is determined by the
user. LD is high when the VCXO PLL phase detector error
is below the user-defined threshold. This threshold is set by
external components RLD and CLD shown in the Lock
Detection Circuit Diagram, below.
To help guard against false lock indications, the LD pin will
go high only when the phase error is below the set threshold
for 8 consecutive phase detector cycles. The LD pin will go
low when the phase error is above the set threshold for only
1 phase detector cycle.
The lock detector threshold (phase error) is determined by
the following relationship:
Lock Detector Application example:
IDT™ / ICS™ VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION 10
MK2069-03
VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION
(LD Threshold) = 0.6 x R x C
Where:
The desired maximum allowable loop phase error for a
generated 19.44MHz clock is 100UI which is 5.1 s.
Solution: 5.1 s = (0.001 f) x (8.5 k
1 k < R < 1 M (to avoid excessive noise or leakage)
C > 50 pF (to avoid excessive error due to stray
capacitance, which can be as much as 10 pF
including Cin of LDC)
Under ideal conditions, where the VCXO is phase- locked to
a low-jitter reference input, loop phase error is typically
maintained to within a few nanoseconds.
Lock Detection Circuit Diagram
If the lock detection circuit is not used, the LDR output may
remain unconnected, however the LDC input should be tied
high or low. If the PCB was designed to accommodate the
RLD and CLD components but the LD output will not be
used, RLD can remain unstuffed and CLD can be replaced
with a resistor (< 10 kohm).
Power Supply Considerations
As with any integrated clock device, the MK2069-03 has a
special set of power supply requirements:
•
The feed from the system power supply must be filtered
for noise that can cause output clock jitter. Power supply
noise sources include the system switching power supply
or other system components. The noise can interfere with
device PLL components such as the VCO or phase
detector.
D e te c to r
D iv id e r
O u tp u t
O u tp u t
P h a s e
V C X O
E rro r
F V
C L D
R L D
L o c k D e te ctio n C irc u it
L D R
(8 u p , 1 d o w n )
Q u a lific a tio n
L D C
C o u n te r
L o c k
VCXO AND SYNTHESIZER
R E S E T
MK2069-03
In p u t T h res h o ld
se t to V D D /2
REV J 030906
L D
O E L