pll102-109 PhaseLink Corp., pll102-109 Datasheet
pll102-109
Related parts for pll102-109
pll102-109 Summary of contents
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... Support 2-wire serial bus interface. 2.5V Operating Voltage. Available in 28-Pin 209mil SSOP. DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK_INT ...
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... PLL for IN synchronization with CLK_INT to eliminate phase error. I/O Serial data input for serial interface port. IN CLK_INC CLKT PLL102-109 Preliminary Description OUTPUTS CLKC FB_OUTT Rev 02/26/03 Page 2 PLL State ...
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... Programmable DDR Zero Delay Clock Driver Default Description - Reserved - Reserved 1 CLKT5, CLKC5 (1= active, 0=inactive) 1 CLKT4, CLKC4 (1= active, 0=inactive) 1 CLKT3, CLKC3 (1= active, 0=inactive) 1 CLKT2, CLKC2 (1= active, 0=inactive) 1 CLKT1, CLKC1 (1= active, 0=inactive) 1 CLKT0, CLKC0 (1= active, 0=inactive) PLL102-109 Preliminary Rev 02/26/03 Page 3 ...
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... These three bits will adjust timing of DDRC signals (CLK2, CLK3, CLK4) either positive or negative delay up to +400ps or –300ps 1 with 100ps per step. (see Table Reserved - - Reserved - - Reserved PLL102-109 Preliminary FBOUT Skew Setting ( 200ps/step) +800ps +600ps +400ps Setting applies to the following out- +200ps puts: Default 1. FB_OUTT -200ps -400ps -600ps ...
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... These four bits will program the propagation delay from CLK_INT 0 to the input of PLL within the range between 0ps and 2.5ns with 0 170ps step size. (see Table 2) 0 +2,550 ps +2,380 ps +2,210 ps +2,040 ps +1,870 ps +1,700 ps +1,530 ps +1,360 ps +1,190 ps +1,020 ps +850 ps +680 ps +510 ps +340 ps +170 ps Default PLL102-109 Preliminary Description Rev 02/26/03 Page 5 ...
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... These three bits will program drive strength for CLK0, CLK1 and 1 CLK5 output clocks (see Table 3 Reserved - - Reserved - - Reserved Default 1 Reserved. 1 Reserved. 0 These three bits will program drive strength for CLK2, CLK3 and 1 CLK4 output clocks (see Table 3 Reserved - - Reserved - - Reserved PLL102-109 Preliminary Description Description Rev 02/26/03 Page 6 ...
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... Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Programmable DDR Zero Delay Clock Driver Default 1 Reserved. 1 Reserved. 1 Reserved. 1 Reserved. 1 Reserved. 0 These three bits will program drive strength for FBOUTT output 1 clock (see Table 3). 1 PLL102-109 Preliminary Description Rev 02/26/03 Page 7 ...
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... VDD=2.7V, V =VDD or GND OZ OUT I = -18mA VDD or GND VDD or GND OUT O VDD = Min to Max VDD = 2.3V -12mA OH VDD = Min to Max VDD = 2.3V 12mA PLL102-109 Preliminary MIN. MAX. - 3 0 0 -65 150 0.7 MIN. TYP. 250 ...
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... T cyc-cyc 100/133/200/266MHz (phase error) All differential input and output terminals are terminated with T oskew 120 16pF T pskew 66MHz to 100MHz D T 101MHz to 266MHz t t Load = 120 16pF r, f PLL102-109 Preliminary MIN. TYP. MAX. 2.3 2.5 2.7 2.3 2.5 2 MIN. MAX. 66 266 40 60 0.1 MIN. ...
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... Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Programmable DDR Zero Delay Clock Driver 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL102-109 X C PLL102-109 Preliminary Package SSOP (QSOP) 209mil Pins Unit ...