pll102-15 PhaseLink Corp., pll102-15 Datasheet

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pll102-15

Manufacturer Part Number
pll102-15
Description
Low Skew Output Buffer - Phaselink Corporation
Manufacturer
PhaseLink Corp.
Datasheet
FEATURES
DESCRIPTIONS
The PLL102 -15 is a high performance, low skew, low
jitter zero delay buffer designed to di stribute high
speed clocks and is available in 8 -pin SOIC or TSSOP
package. It has four outputs that are synchronized with
the input. The synchronization is established via
CLKOUT feedback to the input of the PLL. Since the
skew b etween the input and outpu t is less than 350
ps, the device acts as a zero delay buffer.
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Frequency range 25 ~ 60MHz.
Internal phase locked loop will allow spread spec -
trum modulation on reference clock to pass to the
outputs (up to 33kHz SST modulation).
Zero input - output delay.
Less than 700 ps device - device skew.
Less than 250 ps skew between outputs.
Less than 200 ps cycle - cycle jitter.
Output Enable function tri -state outputs.
3.3V operation.
Available in 8 -Pin 150mil SOIC.
REF_IN
PLL
PIN CONFIGURATION
Remark
If REF_IN clock is stopped for more than 10us after it has already been
provided to the chip, and after power-up, the output clocks will
disappear. In that instance, a full power-up reset is required in order
to reactivate the output clocks.
CLKOUT
CLK1
GND
VDD
Low Skew Output Buffer
CLKOUT
CLK1
CLK2
CLK3
1
2
3
4
8
7
6
5
PLL102-15
N/C
CLK3
REF_IN
CLK2
Rev 05/06/03 Page 1

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pll102-15 Summary of contents

Page 1

... If REF_IN clock is stopped for more than 10us after it has already been provided to the chip, and after power-up, the output clocks will disappear. In that instance, a full power-up reset is required in order to reactivate the output clocks. CLKOUT PLL CLK1 CLK2 CLK3 PLL102-15 8 N/C 7 CLK3 6 CLK2 5 REF_IN ...

Page 2

... Buffered clock output. Internal fe ed back on this pin. P Ground. Input reference frequency. Spread spectrum modulation on this signal will be I passed to the output (up to 33kHz SST modulation). O Buffered clock output. O Buffered clock output connection. PLL102-15 Low Skew Output Buffer Description Rev 05/06/03 Page 2 ...

Page 3

... 50mA 50mA REF = 0MHz DD Unloaded outputs at 60MHz SEL inputs GND DD PLL102-15 Low Skew Output Buffer MIN. MAX 0 0 0 260 - 65 150 MIN ...

Page 4

... CLKOUT pins of devices Loaded outputs cyc -cyc Stable power supply, valid loc k clock presented on REF pin At 10,000 cycles, C =30pF jabs 10,000 cycles, C =30pF Output - Output Skew Output 1.4V Output PLL102-15 Low Skew Output Buffer MIN. TYP. MAX 40.0 50.0 60.0 45.0 50.0 55.0 1.2 1.5 1.2 1.5 250 0 350 ...

Page 5

... Input to Output Propagation Delay Input Output T delay Device to Device Skew Device1 CLKOUT Device2 CLKOUT 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 3.3V 2.0V 0. dsk - dsk PLL102-15 Low Skew Output Buffer Rev 05/06/03 Page 5 ...

Page 6

... CLKOUT CLK(1-3) Delayed REF_IN input and CLK(1-3) outputs loaded equally, with CLK(1-3) more loaded than CLKOUT. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 PLL102-15 Low Skew Output Buffer REF_IN CLKOUT CLK(1-3) Advanced REF_IN and CLK(1-3) outputs loaded equally, with CLK(1-3) less loaded than CLKOUT ...

Page 7

... Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 SOIC Max. 1.73 0.18 0.49 0.25 4.98 3.99 6.20 0.89 A 1.27 BSC 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492 - 0990 Fax: (510) 492- 0991 PART NUMBER PLL102- PLL102-15 Low Skew Output Buffer TEMPERATURE C=COMMERCIAL (0 ~ PACKAGE TYPE S=SOIC Rev 05/06/03 Page 7 ...

Page 8

... Switching Characteristics section on page 4 05/06/03 Bonding diagram modification to P102 -15 (ICS553 compatible) 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Low Skew Output Buffer ) from Unloaded outputs at “66.67MHz” to “60MHz” on page 3 DD PLL102-15 Rev 05/06/03 Page 8 ...

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