pll102-15 PhaseLink Corp., pll102-15 Datasheet - Page 4

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pll102-15

Manufacturer Part Number
pll102-15
Description
Low Skew Output Buffer - Phaselink Corporation
Manufacturer
PhaseLink Corp.
Datasheet
3. Switching Characteristics
SWITCHING WAVEFORMS
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Output Frequency
Duty Cycle ( t2
Duty Cycle ( t2
Rise Time
Fall Time
Output to Output Skew
Delay, REF Rising Edge to
CLKOUT Rising Edge
Device to Device Skew
Cycle to Cycle Jitter
PLL Lock Time
Jitter; Absolute Jitter
Jitter; 1- sima
Duty Cycle Timing
PARAMETERS
1.4V
t1 )
t1 )
t2
1.4V
t1
SYMBOL
T
T
T
T
T
T
dsk -dsk
cyc -cyc
T
Dt1
Dt2
delay
T
T
skew
t1
loc k
jabs
j1 -s
1.4V
r
f
Measured at 1.4V,
C
Measured at 1.4V
Measured between 0.8V
and 2.0V, C
Measured between 2.0V
and 0.8V, C
All outputs equally loaded,
C
Measured at 1.4V
Measured at V
CLKOUT pins of devices
Loaded outputs
Stable power supply, valid
clock presented on REF pin
At 10,000 cycles, C
At 10,000 cycles, C
L
L
=30pF, F
=20p F
DESCRIPTION
out
L
L
=30pF
=30pF
Output - Output Skew
= 60MHz
Output
Output
DD
/2 on the
L
L
=30pF
=30pF
1.4V
MIN.
40.0
45.0
- 100
T
25
SKEW
Low Skew Output Buffer
1.4V
TYP.
50.0
50.0
1.2
1.2
70
14
0
0
PLL102-15
MAX.
60.0
55.0
250
700
200
100
Rev 05/06/03 Page 4
1.5
1.5
1.0
60
350
30
UNITS
M H z
ms
ns
ns
ps
ps
ps
ps
ps
ps
%
%

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