hd74ls191 Renesas Electronics Corporation., hd74ls191 Datasheet

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hd74ls191

Manufacturer Part Number
hd74ls191
Description
Synchronous Up / Down 4-bit Binary Counter Single Clock Line
Manufacturer
Renesas Electronics Corporation.
Datasheet
HD74LS191
Synchronous Up / Down 4-bit Binary Counter (single clock line)
Synchronous operation is provided by having all flip-flops clocked simultaneously so that the steering logic. This mode
of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters. The
outputs of the four master-slave flip-flops are triggered on a low-to-high-level transition of the clock input if the enable
input is high. The direction of the count is determined by the level of the down / up input. When low, the counter
counts up and when high, it counts down. Level changes at the down / up input should be made only when the clock
input is high. This counter is fully programmable; that is, the outputs may be preset to either level by placing a low on
the load input and entering the desired data at the data inputs. The output will change to agree with the data inputs
independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by
simply modifying the count length with the preset inputs. The clock, down / up, and load inputs are buffered to lower
the drive requirement which significantly reduces the number of clock drivers, etc., required for long parallel words.
Two outputs have been made available to perform the cascading function; ripple clock and made available to perform
the cascading function; ripple clock and maximum / minimum count. The latter output produces a high-level output
pulse with a duration approximately equal to one complete cycles to the clock when the counter overflows or
underflows. The ripple clock output produces a low-level output pulse equal in width to the low-level portion of the
clock input when an overflow or underflow condition exists.
The counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if
parallel clocking is used, or to the clock input if parallel enabling is used. The maximum / minimum count output can
be used to accomplish look-ahead for high-speed operation.
Features
Note: Please consult the sales office for the above package availability.
Rev.2.00, Feb.18.2005, page 1 of 10
Part Name
HD74LS191P
HD74LS191FPEL
Ordering Information
Package Type
DILP-16 pin
SOP-16 pin (JEITA)
Package Code
(Previous Code)
PRDP0016AE-B
(DP-16FV)
PRSP0016DH-B
(FP-16DAV)
Package
Abbreviation
P
FP
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
REJ03D0453–0200
Feb.18.2005
Rev.2.00

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hd74ls191 Summary of contents

Page 1

... Features Ordering Information Part Name Package Type HD74LS191P DILP-16 pin HD74LS191FPEL SOP-16 pin (JEITA) Note: Please consult the sales office for the above package availability. Rev.2.00, Feb.18.2005, page Package Code Package (Previous Code) ...

Page 2

... HD74LS191 Pin Arrangement Data B Input Outputs Enable G Inputs Down/Up Outputs GND Rev.2.00, Feb.18.2005, page Ripple G 4 Clock Max/ 5 Dn/Up Min Load (Top view Data A Inputs ...

Page 3

... HD74LS191 Block Diagram Clock Down/Up Data Input A Enable G Data Input B Data Input C Data Input D Load Absolute Maximum Ratings Item Supply voltage Input voltage Power dissipation Storage temperature Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Rev.2.00, Feb.18.2005, page ...

Page 4

... HD74LS191 Recommended Operating Conditions Item Supply voltage Output current Operating temperature Clock frequency Clock pulse width Load pulse width Setup time Hold time Enable time Electrical Characteristics Item Symbol V IH Input voltage Output voltage V OL Enable I IH Others Enable ...

Page 5

... HD74LS191 Switching Characteristics Item Symbol Maximum clock max frequency t PLH t PHL t Data A, PLH t PHL t PLH t PHL t PLH t Propagation PHL delay time t PLH t PHL t PLH t PHL t PLH t PHL t PLH t PHL Rev.2.00, Feb.18.2005, page Inputs Outputs min. Clock ...

Page 6

... HD74LS191 Count Sequences Load Clock Down/Up Enable Max/Min Ripple Clock 13 Load Illustrated below is the following sequence: 1. Load (preset) to binary thirteen. 2. Count up to fourteen, fifteen (maximum), zero, one and two. 3. Inhibit 4. Count down to one, zero (minimum), fifteen, fourteen, and thirteen. ...

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... HD74LS191 Testing Method Test Circuit 4.5V Input P. 50Ω out Notes includes probe and jig capacitance. 2. All diodes are 1S2074(H). Waveforms 1 t TLH Data Input 10% Load Input Output Note: Input pulse ns, PRR = 1 MHz, duty cycle TLH THL Rev.2.00, Feb.18.2005, page ...

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... HD74LS191 Waveforms 2 Load Q, Data Q Load Data ( Output Q Note: Conditions on other inputs are irrelevant. Waveforms 3 G Ripple CK, CK Ripple CK, Down / Up Ripple CK, Down / Up Max / Min Load Down/Up Clock G Ripple/Clock Max/Min Rev.2.00, Feb.18.2005, page 1.3V 1.3V 1.3V 1.3V 1. PLH PHL PLH 1.3V 1. PHL PLH 1 ...

Page 9

... HD74LS191 Waveforms 4 Clock Q Load Data ( Down/Up Clock Q Enable = 0V Waveforms 5 Clock Max / Min Load A Inputs Down/Up Clock Max/Min Enable = 0V Rev.2.00, Feb.18.2005, page 1.3V 1.3V t PLH 1.3V 1.3V 1.3V 1. PLH PHL PLH 1. 1. PHL ...

Page 10

... HD74LS191 Package Dimensions JEITA Package Code RENESAS Code P-DIP16-6.3x19.2-2.54 PRDP0016AE 0. JEITA Package Code RENESAS Code P-SOP16-5.5x10.06-1.27 PRSP0016DH Index mark Rev.2.00, Feb.18.2005, page Previous Code MASS[Typ.] DP-16FV 1.05g Previous Code MASS[Typ ...

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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...

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