hd74ls669 Renesas Electronics Corporation., hd74ls669 Datasheet

no-image

hd74ls669

Manufacturer Part Number
hd74ls669
Description
Synchronous Up / Down 4-bit Binary Counter
Manufacturer
Renesas Electronics Corporation.
Datasheet
HD74LS669
Synchronous Up / Down 4-bit Binary Counter
This synchronous preset table 4-bit binary counter features an internal carry look-ahead for cascading in high-speed
counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the
outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode
of operation helps eliminate the output counting spikes that are normally associated with asynchronous (ripple-clock)
counters. A buffered clock input trigger the four master-slave flip-flops on the rising (positive-going) edge of the clock
waveform. This counter is fully programmable; that is, the outputs may each be preset to either level. the load input
circuitry allows loading with the carry-enable output of cascaded counters. As loading is synchronous, setting up a low
level at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional
gating. Instrumental in accomplishing this function are two count enable inputs and a carry output. Both count enable
inputs (P and T) must be low to count. The direction of the count is determined by the level of the up / down input.
when the input is high, the counter counts up; when low, it counts down. Input T is fed forward to enable the carry
output. The carry output thus enabled will produce a low-level output pulse with a duration approximately equal to the
high portion of the Q
counting down. This low level overflow carry pulse can be used to enable successive cascaded stages.
Transitions at the enable P or T inputs are allowed regardless of the level of the clock input. All inputs are diode-
clamped to minimize transmission-line effects, thereby simplifying system design. This counter features a fully
independent clock circuit. Changes at control inputs (enable P, enable T, load, up / down) that will modify the
operating mode have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading,
or counting) will be dictated solely by the conditions meeting the stable setup and hold times.
Features
Note: Please consult the sales office for the above package availability.
Rev.2.00, Feb.18.2005, page 1 of 8
Part Name
HD74LS669FPEL
Ordering Information
A
Package Type
SOP-16 pin (JEITA)
output when counting up and approximately equal to the low portion of the Q
Package Code
(Previous Code)
PRSP0016DH-B
(FP-16DAV)
Package
Abbreviation
FP
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
REJ03D0493–0200
A
output when
Feb.18.2005
Rev.2.00

Related parts for hd74ls669

hd74ls669 Summary of contents

Page 1

... Features Ordering Information Part Name Package Type HD74LS669FPEL SOP-16 pin (JEITA) Note: Please consult the sales office for the above package availability. Rev.2.00, Feb.18.2005, page Package Code ...

Page 2

... HD74LS669 Pin Arrangement U/D Data Inputs Enable P GND Block Diagram Clock U/D Load Enable P Enable T Data A Data B Data C Data D Rev.2.00, Feb.18.2005, page (Top view Ripple 15 Carry Output Outputs ...

Page 3

... HD74LS669 Absolute Maximum Ratings Item Supply voltage Input voltage Power dissipation Storage temperature Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Recommended Operating Conditions Item Supply voltage Output current Operating temperature Count frequency Clock pulse width Input Data ...

Page 4

... HD74LS669 Switching Characteristics Item Symbol Maximum clock frequency max t PLH t PHL t PLH t PHL Propagation delay time t PLH t PHL t PLH t PHL Count Sequence Load A B Data Inputs C D Clock U/D P and Ripple Carry 13 Output Load Rev.2.00, Feb.18.2005, page ...

Page 5

... HD74LS669 Testing Method Test Circuit 4.5V Input P. 50Ω out Input P. 50Ω out Notes includes probe and jig capacitance All diodes are 1S2074(H). Rev.2.00, Feb.18.2005, page Output U/D Output CK Q Same as Load Circuit ...

Page 6

... HD74LS669 Waveforms 1 t THL 90% Clock 1.3V 10% 10% Load 1.3V Data Inputs 1. Enable P or Enable T Up/Down Enable T 1.3V Input t PHL Ripple Carry Output from enable T input to ripple carry output assume that the counter is at the Notes and t PLH PHL maximum count (Q 2. Propagation delay time from up / douwn to ripple carry must be measured with the counter at either aminimum or a maximum count ...

Page 7

... HD74LS669 Waveforms TLH THL 90% Clock 1.3V 1.3V 10% (Measure PLH (Measure before PLH 1 clock of t Ripple 1.3V Carry Output Notes: 1. Input pulse; t TLH 2. For max TLH THL the bit-time when all outputs are low. n Rev.2.00, Feb.18.2005, page ...

Page 8

... HD74LS669 Package Dimensions JEITA Package Code RENESAS Code P-SOP16-5.5x10.06-1.27 PRSP0016DH Index mark Rev.2.00, Feb.18.2005, page Previous Code MASS[Typ.] FP-16DAV 0.24g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET ...

Page 9

Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...

Related keywords