74lv259 NXP Semiconductors, 74lv259 Datasheet - Page 10

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74lv259

Manufacturer Part Number
74lv259
Description
8-bit Addressable Latch
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
74LV259_3
Product data sheet
Fig 9. The conditional reset input (MR) to output (Qn) propagation delays
Fig 10. The data set-up and hold times for the D input to the LE input
Fig 11. The address input set-up and hold times for the An inputs to the LE input
Measurement points are given in
V
Measurement points are given in
V
Measurement points are given in
V
OL
OL
OL
and V
and V
and V
OH
OH
OH
are typical voltage output levels that occur with the output load.
are typical voltage output levels that occur with the output load.
are typical voltage output levels that occur with the output load.
Qn output
LE input
D input
An input
LE input
Qn output
MR input
Table
Table
Table
GND
GND
V
V
GND
GND
V
V
V
V
CC
CC
OH
CC
CC
OL
9.
9.
9.
GND
V
V
V
CC
OH
OL
Rev. 03 — 2 January 2008
Q = D
V
t
su
M
V
M
V
V
t
M
ADDRESS STABLE
M
t
su
PHL
t
W
t
V
h
M
V
M
V
M
t
h
001aah124
t
Q = D
su
001aah126
001aah125
t
h
8-bit addressable latch
© NXP B.V. 2008. All rights reserved.
74LV259
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