max5863 Maxim Integrated Products, Inc., max5863 Datasheet
max5863
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max5863 Summary of contents
Page 1
... The MAX5863 features an internal 1.024V voltage reference that is stable over the entire operating power-supply range and temperature range. The MAX5863 operates on a +2.7V to +3.3V ana- log power supply and a +1.8V to +3.3V digital I/O power supply for logic compatibility. The quiescent current is 3.5mA in idle mode and 1µA in shutdown mode. The MAX5863 is specified for the extended (-40° ...
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Ultra-Low-Power, High-Dynamic Performance, 7.5Msps Analog Front End ABSOLUTE MAXIMUM RATINGS V to GND OGND................................-0.3V to +3. GND to OGND.......................................................-0.3V to +0.3V IA+, IA-, QA+, QA-, ID+, ID-, QD+, QD-, REFP, REFN, REFIN, COM to GND ..............................-0.3V ...
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Performance, 7.5Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C otherwise noted. Typical values are ...
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Ultra-Low-Power, High-Dynamic Performance, 7.5Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C otherwise noted. Typical values are at ...
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Performance, 7.5Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C otherwise noted. Typical values are ...
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Ultra-Low-Power, High-Dynamic Performance, 7.5Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C otherwise noted. Typical values are at ...
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... A guaranteed by design and characterization. Note 2: The minimum clock frequency for the MAX5863 is 2MHz. Note 3: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude of the digital outputs. SINAD and THD are calculated using HD2 through HD6. ...
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Ultra-Low-Power, High-Dynamic Performance, 7.5Msps Analog Front End ( 3V 1.8V, internal reference (1.024V input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output ...
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Performance, 7.5Msps Analog Front End ( 3V 1.8V, internal reference (1.024V input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output 0.33µF, Xcvr ...
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Ultra-Low-Power, High-Dynamic Performance, 7.5Msps Analog Front End ( 3V 1.8V, internal reference (1.024V input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output ...
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Performance, 7.5Msps Analog Front End ( 3V 1.8V, internal reference (1.024V input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output 0.33µF, Xcvr ...
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Ultra-Low-Power, High-Dynamic Performance, 7.5Msps Analog Front End PIN NAME 1 REFP Upper Reference Voltage. Bypass with a 0.33µF capacitor to GND as close to REFP as possible. Analog Supply Voltage. Bypass 0.1µF capacitor. 3 ...
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... DAC can be shared to reduce the digital I single 10-bit parallel multiplexed bus. In FDD mode, the full-scale signals. P-P MAX5863 digital I/O can be configured for an 18-bit, parallel multiplexed bus to match the dual 8-bit ADC and dual 10-bit DAC. The MAX5863 features an internal precision 1.024V bandgap reference output and is stable over the entire power-supply and temperature ranges ...
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... MAX5863 and degrading its dynamic performance. Buffers on the digital outputs isolate them from heavy capacitive loads. Adding 100Ω resistors in series with the digital outputs close to the MAX5863 helps improve ADC performance. Refer to the MAX5865 EV kit schematic for an example of the digital outputs driving a digital buffer through 100Ω ...
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... This simplifies the analog interface between RF quadrature upconverters and the MAX5863. RF upconverters require a 1.3V to 1.5V com- mon-mode bias. The internal DC common-mode bias eliminates discrete level-setting resistors and code-gen- erated level-shifting while preserving the full dynamic range of each transmit DAC ...
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... N-1 N-2 N-1 The 3-wire serial interface controls the MAX5863 opera- tion modes. Upon power-up, the MAX5863 must be programmed to operate in the desired mode. Use the 3-wire serial interface to program the device for the shutdown, idle, standby, Rx, Tx, or Xcvr mode. An 8-bit data register sets the operation modes as shown in Table 3 ...
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... Shutdown mode offers the most dramatic power sav- ings by shutting down all the analog sections of the MAX5863 and placing the ADCs’ digital outputs in tri- state mode. When the ADCs’ outputs transition from tri- state to on, the last converted word is placed on the digital outputs. The DACs’ ...
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... SINAD performance and DAC settling to 10 LSB error times are measured after the 8-bit WAKE ENABLE serial command is latched into the MAX5863 by CS transition high. t for Xcvr mode is dominated by ENABLE the DAC wake-up time. The recovery time is 10µs to switch between Xcvr, Tx modes. The recovery time is 40µ ...
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... V former can be used step-up transformer can be selected to reduce the drive requirements. In general, the MAX5863 provides better SFDR and THD with fully differential input signals than single-ended signals, especially for high-input frequencies. In differential mode, even-order harmonics are lower as both inputs ...
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... ADC and 10-bit DAC) to the digital baseband processor. Select Xcvr mode through the 3-wire serial interface and use the conver- sion clock to latch data. In FDD mode, the MAX5863 INA- uses 21mW power at f power of the ADC and DAC operating simultaneously. ...
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... R10 R11 600Ω 600Ω ADC MAX2391 ADC QUADRATURE OUTPUT DEMODULATOR MUX ADC DAC MAX2395 DAC QUADRATURE INPUT TRANSMITTER MUX DAC MAX5863 MAX5863 R ISO 22Ω INA 5pF COM R ISO 22Ω INA 5pF CLK CLK 10 BIT SERIAL BUS 21 ...
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... Also, the DAC’s full dynamic range is pre- served because the internally generated common- mode level eliminates code-generated level shifting or attenuation due to resistor level shifting. The MAX5863 ADC has 1V full-scale range and accepts input com- P-P mon-mode levels (± ...
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Performance, 7.5Msps Analog Front End Ideally, the midscale transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured transition point and the ideal transition point. Offset error is the difference between the ...
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... IA+ 3 IA- 4 GND 5 CLK 6 GND QA GND 12 2 n 1 through 2 TRANSISTOR COUNT: 16,765 PROCESS: CMOS Pin Configuration SCLK 34 DIN DD9 31 DD8 MAX5863 30 DD7 29 DD6 28 DD5 27 DD4 DD3 26 DD2 25 QFN Chip Information ...
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Performance, 7.5Msps Analog Front End (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) D D/2 ______________________________________________________________________________________ Ultra-Low-Power, High-Dynamic k E/2 (NE- DETAIL ...
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Ultra-Low-Power, High-Dynamic Performance, 7.5Msps Analog Front End (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) COMMON DIMENSIONS Maxim cannot assume responsibility for use of any ...