cs5322-blz Cirrus Logic, Inc., cs5322-blz Datasheet - Page 23

• Manufacturer Part Number: cs5322-blz
• Description: 24-bit, Variable-bandwidth A/d Converter Chipset
• Manufacturer: Cirrus Logic, Inc.

2.9 Power Supply Considerations
The system connection diagram, Figure 20, illus-
trates the recommended power supply arrange-
ments. There are two positive power supply pins
for the CS5321 and two negative power supply
pins. Power must be supplied to all four pins and
each of the supply pins should be de-coupled with
a 0.1 µF capacitor to the nearest ground pin on the
device.
When used with the CS5322 digital filter, the max-
imum voltage differential between the positive sup-
plies of the CS5321 and the positive digital supply
of the CS5322 must be less than 0.25 V. Operation
beyond this constraint may result in loss of analog
performance in the CS5321/22 system perfor-
mance.
Many seismic or portable data acquisition systems
are battery powered and utilize dc-dc converters to
generate the necessary supply voltages for the sys-
tem. To minimize the effects of power supply inter-
ference, it is desirable to operate the dc-dc
converter at a frequency which is rejected by the
digital filter, or locked to the modulator sample
clock rate.
A synchronous dc-dc converter, whose operating
frequency is derived from the 1.024 MHz clock
used to drive the CS5322, will minimize the poten-
tial for "beat frequencies" appearing in the pass-
band between dc and the corner frequency of the
digital filter.
2.10 Power Supply Rejection Ratio
The PSRR of the CS5321 is frequency dependent.
The CS5322 digital filter attenuation will aid in re-
jection of power supply noise for frequencies
above the corner frequency setting of the CS5322.
For frequencies between dc and the corner frequen-
cy of the digital filter, the PSRR is nearly constant
at about 60 dB.
DS454F3
2.11 RESET Operation
The RESET pin puts the CS5322 into a known ini-
tialized state. RESET is recognized on the next
CLKIN rising edge after the RESET pin has been
brought high (RESET=1). All internal logic is ini-
tialized when RESET is active.
Normal device operation begins on the second
CLKIN rising edge after RESET is brought low.
The CS5322 will remain in an idle state, not per-
forming convolutions, until triggered by a SYNC
event.
A RESET operation clears memory, sets the data
output register, offset register, and status flags to all
zeroes, and sets the configuration register to the
state of the corresponding hardware pins (PWDN,
ORCAL, DECC, DECB, DECA, USEOR, and
CSEL). The reset state is entered on power on, in-
dependent of the RESET pin. If RESET is low, the
first CLKIN will exit the power on reset state.
2.12 Power-down Operation
The PWDN pin puts the CS5322 into the power-
down state. The power-down state is entered on the
first CLKIN rising edge after the PWDN pin is
brought high. While in the power-down state, the
MCLK and MSYNC signals to the CS5321 analog
modulator are held low. The loss of the MCLK sig-
nal to the modulator causes it to power-down. The
signals on the MDATA and MFLG pins are ig-
nored. The serial interface of the CS5322 remains
active allowing read and write operations. Informa-
tion in the data register, offset register, configura-
tion register, and convolution data memory are
maintained during power-down. The internal con-
troller requires 64 clock cycles after PWDN is as-
serted before CLKIN stops.
The CS5322 exits the power-down state on the first
CLKIN rising edge after the PWDN pin is brought
low. The CS5322 then enters an idle state until trig-
gered by a SYNC event.
CS5321/22
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