cs5323gdw20 ON Semiconductor, cs5323gdw20 Datasheet - Page 12

• Manufacturer Part Number: cs5323gdw20
• Description: Three-phase Buck Controller With 5-bit Dac
• Manufacturer: ON Semiconductor

order to reduce voltage excursions during transients.
Adaptive voltage positioning can reduce peak−peak output
voltage deviations during load transients and allow for a
smaller output filter. The output voltage can be set higher at
light loads to reduce output voltage sag when the load
current is stepped up and set lower during heavy loads to
reduce overshoot when the load current is stepped up. For
low current applications a droop resistor can provide fast
accurate adaptive positioning. However at high currents, the
loss in a droop resistor becomes excessive. For example; in
a 50 A converter a 1 mΩ resistor to provide a 50 mV change
in output voltage between no load and full load would
dissipate 2.5 Watts.
droop resistor, but must respond quickly to changes in load
current. Figure 10 shows how adaptive positioning works.
The waveform labeled normal shows a converter without
adaptive positioning. On the left, the output voltage sags
when the output current is stepped up and later overshoots
when current is stepped back down. With fast (ideal)
adaptive positioning the peak to peak excursions are cut in
half. In the slow adaptive positioning waveform the output
voltage is not repositioned quickly enough after current is
stepped up and the upper limit is exceeded.
accurate adaptive positioning. For low frequency
positioning the V
output voltage with varying load currents. For high
frequency positioning, the current sense input pins can be
used to control the power stage output impedance. The
transition between fast and slow positioning is adjusted by
the error amp compensation.
voltage based on the output current of the converter. The
adaptive positioning circuit is designed to select the DAC
setting as the maximum output voltage. (Refer to Figure 1 on
page 2.)
between the output voltage and V
current will develop a voltage across the resistor to decrease
the output voltage. The V
value of ROSC. See Figure 4 on the datasheet.
voltage as the V
through the V
Lossless adaptive positioning is an alternative to using a
The CS5323 uses two methods to provide fast and
The CS5323 can be configured to adjust the output
To set the no−load positioning a resistor (R9) is placed
During no load conditions the V
Figure 10. Adaptive Positioning
Normal
Slow
Limits
Fast
FB
DRP
Adaptive Positioning
Adaptive Positioning
FB
pin, so none of the V
resistor (R6). When output current
and V
FB
DRP
bias current is dependent on the
pins are used to adjust the
DRP
FB
FB
pin. The V
pin is at the same
bias current flows
FB
http://onsemi.com
bias
12
increases the V
V
output voltage to further decrease.
voltage positioning. The first few μs are controlled primarily
by the ESR and ESL of the output filter. The transition
between fast and slow positioning is controlled by the ramp
size and the error amp compensation. If the ramp size is too
large or the error amp too slow there will be a long transition
to the final voltage after a transient. This will be most
apparent with lower capacitance output filters.
width jitter.
Error Amp Compensation
provide both a slow soft−start and a fast transient response.
C4 in the main applications diagram controls soft−start. A
0.1 μF capacitor with the 30 μA error amplifier output
capability will allow the output to ramp up at 0.3 V/ms or
1.5 V in 5 ms.
amplifier to slew quickly over a narrow range during load
transients. Here the 30 μA error amplifier output capability
works against 8 kΩ (R10) to limit the window of fast slewing
too 240 mV − enough to allow for fast transients, but not
enough to interfere with soft−start. This window will be
noticeable as a step in the COMP pin voltage at start−up. The
size of this step must be kept smaller than the Channel
Start−Up Offset (nominally 0.4 V) for proper soft−start
operation. If adaptive positioning is used the R9 and R8 form
a divider with the V
start−up, which effectively makes the Channel Start−Up
Offset larger.
is required on the error amp output. Use of values less than
1 nF may result in error amp oscillation of several MHz.
and the V
gain. C28 adds a zero to the error amp response to boost the
phase near the crossover frequency.
UVLO
connected to the V
converter is powered from multiple voltages, additional
UVLO protection might be required if the voltage powering
the controller can turn on before other voltages.
function monitors the 5.0 V supply. If the 5.0 V supply
comes up before the 12 V supply, the COMP pin will rise
until it reaches the upper rail or until the 12 V supply comes
up and the converter comes into regulation. If the delay
between the 5.0 V and 12 V supplies is too long, soft−start
will be compromised. A diode connected from the 12 V
supply to the COMP pin can hold the COMP pin down until
the 12 V supply starts to come up. Or, if a higher UVLO
DRP
The V
Note: Large levels of adaptive positioning can cause pulse
The transconductance error amplifier can be configured to
R10 is connected in series with C4 to allow the error
C12 is included for error amp stability. A capacitive load
C11 and the parallel resistance of the V
The CS5323 has one undervoltage lockout function
For the 12 V
pin current offsets the V
FB
DRP
and V
resistor (R6) are used to roll off the error amp
IN
DRP
converter in Figure 1, the CS5323 UVLO
DRP
DRP
pin increases proportionally and the
CC
pins take care of the slower and DC
end held at the DAC voltage during
pin. In applications where the
FB
bias current and causes the
FB
resistor (R9)