cs5323gdw20 ON Semiconductor, cs5323gdw20 Datasheet - Page 14

• Manufacturer Part Number: cs5323gdw20
• Description: Three-phase Buck Controller With 5-bit Dac
• Manufacturer: ON Semiconductor

Current Limit
exceeds the voltage on the I
mode. For inductive sensing the I
set based on the inductor resistance (or current sense
resistor) at max temperature and max current. To set the level
of the I
When the sum of the Current Sense amplifiers (V
3. For resistive current sensing choose L and R
4. Calculate the high frequency output impedance
5. Adjust L and R
6.
Then choose the inductor value and inherent resistance
to satisfy L/R
For ideal current sense compensation the ratio of L and
R
compromise typically with the maximum value R
limited by conduction losses or inductor temperature
rise and the minimum value of L limited by ripple
current.
Again the ratio of L and R
L and R
where:
Multiply the converterZ by the output current step size
to calculate where the output voltage should recover to
within the first switching cycle after a transient. If the
ConverterZ is higher than the value required to recover
to where the adaptive positioning is set the remainder
of the recovery will be controlled by the error amp
compensation and will typically recover in 10 − 20 μs.
Make sure that ΔVR is less than the expected peak
transient for a good transient response.
where:
provide a steady state ramp greater than 25 mV.
(ConverterZ) of the converter during transients. This
is the impedance of the Output filter ESR in parallel
with the power stage output impedance (PwrstgZ)
and will indicate how far from the original level
(ΔVR) the output voltage will typically recover to
within one switching cycle. For a good transient
response ΔVR should be less than the peak output
voltage overshoot or undershoot.
combination of transient response, steady state output
voltage ripple and pulse width jitter.
V I(LIM) + R
L
LIM
is fixed, so the values of L and R
L R S + (V IN * V OUT )
pin:
ConverterZ +
S
PwrstgZ + R S
DVR + DI OUT
will be a compromise.
DVR + ConverterZ
L
= R × C.
L
I OUT(LIM)
or R
PwrstgZ
PwrstgZ ) ESR
LIM
S
as required to meet the best
pin the part will enter hiccup
L
CSA Gain 3
ConverterZ
LIM
is fixed and the values of
CS to I LIM Gain
T ON 25 mV
pin voltage should be
ESR
ESR
L
will be a
ITOTAL
http://onsemi.com
S
to
L
)
14
Adaptive Positioning
Calculate Input Filter Capacitor Current Ripple
and output inductor ripple current (P−P) is less than the
average output current of one phase.
I IN +
Duty Cycle +
Apparent Duty Cycle + Duty Cycle
Ripple (RMS) + I IN
10. Calculate Duty Cycle (per phase).
11. Calculate Apparent Duty Cycle.
12. Calculate Input Filter Capacitor Ripple Current. Use
The procedure below assumes that phases do not overlap
7. To set the amount of voltage positioning below the
8. To set the difference in output voltage between no load
9. Calculate Input Current
See Figure 4 for V
where:
For the overcurrent to work properly the inductor time
constant (L/R) should be ≤ the Current sense RC. If the
RC is too fast, during step loads the current waveform
will appear larger than it is (typically for a few hundred
μs) and may trip the current limit at a level lower than
the DC limit.
DAC setting at no load connect a resistor (R
between the output voltage and the V
R
and full load, connect a resistor (R
V
steps. First calculate the difference between the V
and V
the same as the DAC voltage during closed loop
operation.) Then choose the R
current across R
voltage.
the chart in Figure 13 to calculate the normalized
ripple current (K
Apparent Duty Cycle. Then multiply the input current
by K
Current.
( Efficiency
R is R
I
R = R
I
V
OUT(LIM)
DRP
OUTFL
V OUT
R V(DRP) + DV DRP
DV V(DRP) + I OUTFL
(
FB
RMS
FB
R V(FB) + NL Position V FB Bias Current
) as;
and V
L
L
( Efficiency
or R
is the full load output current.
or R
pin at full load. (The V
to obtain the Input Filter Capacitor Ripple
I OUT
is the current limit threshold.
FB
S
S;
V IN )
V OUT
for one phase;
pins. R
V
(
K RMS
FB
FB
RMS
) for the desired change in output
Bias Current.
V(DRP)
V IN )
) based on the reciprocal of
R V(FB) DV OUT
R
can be calculated in two
V(DRP)
FB
# of Phases
V(DRP)
CS to V DRP Gain
voltage should be
to source enough
FB
) between the
pin. Choose
V
(
FB
DRP
))