kad5512p-21 ETC-unknow, kad5512p-21 Datasheet - Page 14

• Manufacturer Part Number: kad5512p-21
• Description: 12-bit, 500msps A/d Converter
• Manufacturer: ETC-unknow

Functional Description
The KAD5512P-50 is based upon a 12-bit, 250MSPS
A/D converter core that utilizes a pipelined succes-
sive approximation architecture (Figure 27). The input
voltage is captured by a Sample-Hold Amplifier (SHA)
and converted to a unit of charge. Proprietary
charge domain techniques are used to successively
compare the input to a series of reference charges.
Decisions made during the successive approximation
operations determine the digital code for each input
value. The converter pipeline requires twelve samples
to produce a result. Digital error correction is also ap-
plied, resulting in a total latency of fifteen clock cy-
cles. This is evident to the user as a latency between
the start of a conversion and the data being avail-
able on the digital outputs.
The device contains two A/D converter cores with
carefully matched transfer characteristics. The cores
are clocked on opposite clock edges, resulting in a
doubling of the sample rate. The gain, offset and
skew errors between the two cores are adjustable via
the SPI port to minimize spurs associated with the in-
terleaving process.
At start-up, each core performs a self-calibration to
minimize gain and offset errors. The reset pin (RESETN)
is initially set high at power-up and will remain in that
state until the calibration is complete. The clock fre-
Rev 0.5.1 Preliminary
KAD5512P-50
Figure 27. ADC Core Block Diagram
quency should remain fixed during this time, and no
SPI communications should be attempted. Recalibra-
tion can be initiated via the SPI port at any time after
the initial self-calibration.
Power-On Calibration
At start-up, the core performs a self-calibration to
minimize gain and offset errors. An internal power-on-
reset (POR) circuit detects the supply voltage ramps
and initiates the calibration when the analog and
digital supply voltages are above a threshold. The
following conditions must be adhered to for the
power-on calibration to execute successfully:
A user-initiated reset can subsequently be invoked in
the event that the above conditions cannot be met
at power-up.
The SDO pin requires an external 4.7kº pull-up to
OVDD. If the SDO pin is pulled low externally during
power-up, calibration will not be executed properly.
x
x
x
x
x
A frequency-stable conversion clock must be
applied to the CLKP/CLKN pins
DNC pins (especially 3, 4 and 18) must not be
pulled up or down
SDO (pin 66) must be high
RESETN (pin 25) must begin low
SPI communications must not be attempted
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