kad5512p-21 ETC-unknow, kad5512p-21 Datasheet - Page 19

• Manufacturer Part Number: kad5512p-21
• Description: 12-bit, 500msps A/d Converter
• Manufacturer: ETC-unknow

or functional parameters. Many registers in the avail-
able address space (0x00 to 0xFF) are not defined in
this document. Additionally, within a defined register
there may be certain bits or bit combinations that
are reserved. Undefined registers and undefined val-
ues within defined registers are reserved and should
not be selected. Setting any reserved register or
value may produce indeterminate results.
SPI Physical Interface
The SPI port operates in a half or full duplex mas-
ter/slave configuration, with the KAD5512P-50 func-
tioning as a slave. Multiple slave devices can inter-
face to a single master. The chip-select bar (CSB) pin
determines when a slave device is being addressed.
Multiple slave devices can be written to concurrently,
but only one slave device can be read from at a
given time. If multiple slave devices are selected for
reading at the same time, the results will be indeter-
minate.
The serial clock pin (SCLK) provides synchronization
for the data transfer. By default, all data is presented
on the serial data input/output (SDIO) pin. The state
of the SDIO pin is set automatically in the communi-
cation protocol (described below). A dedicated se-
rial data output pin (SDO) can be activated by set-
ting 0x00[7] high to allow operation in full duplex
mode.
The communication protocol begins with an instruc-
tion/address phase. The first rising SCLK edge follow-
ing a high to low transition on CSB determines the
Rev 0.5.1 Preliminary
KAD5512P-50
Figure 39. MSB-First Addressing
Figure 40. LSB-First Addressing
beginning of the two-byte instruction/address com-
mand. Data can be presented in MSB-first order or
LSB-first order. The default is MSB-first, but this can be
changed by setting 0x00[6] high. Figures 39 and 40
show the appropriate bit ordering for the MSB-first
and LSB-first modes, respectively. In MSB-first mode
the address is incremented for multi-byte transfers,
while in LSB-first mode it’s decremented.
In the default mode the MSB is R/W, which deter-
mines if the data is to be read (active high) or writ-
ten. The next two bits, W1 and W0, determine the
number of data bytes to be read or written (see Ta-
ble 6). The lower 13 bits contain the first address for
the data transfer. This relationship is illustrated in Fig-
ure 41, and timing values are given in the Switching
Specifications section.
After the instruction/address bytes have been read,
the appropriate number of data bytes are written to
or read from the ADC (based on the R/W bit status).
The data transfer will continue as long as CSB remains
low and SCLK is active. Stalling of the CSB pin is al-
lowed at any byte boundary (instruction/address or
data) if the number of bytes being transferred is three
or less. For transfers of four bytes or more, CSB is al-
lowed stall in the middle of the instruction/address
bytes or before the first data byte. If CSB transitions to
a high state after that point the state machine will
reset and terminate the data transfer.
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