kad5512p-21 ETC-unknow, kad5512p-21 Datasheet - Page 23

• Manufacturer Part Number: kad5512p-21
• Description: 12-bit, 500msps A/d Converter
• Manufacturer: ETC-unknow

overridden and controlled through the SPI, as shown
in Table 14.
This register is not changed by a Soft Reset.
Address 0x74: output_mode_B
Address 0x75: config_status
Bit 6
The output_mode_B and config_status registers are
used in conjunction to enable DDR mode and select
the frequency range of the DLL clock generator. The
method of setting these options is different from the
other registers.
The procedure for setting output_mode_B is shown in
Figure 45. Read the contents of output_mode_B and
config_status and XOR them. Then XOR this result with
the desired value for output_mode_B and write that
XOR result to the register.
DUT Test
The KAD2512 can produce preset or user defined
patterns on the digital outputs to facilitate in-situ test-
Rev 0.5.1
KAD5512P-50
Figure 45. Setting output_mode_B register
DLL Range
This bit sets the DLL operating range to fast
(TBD2MSPS to 250MSPS) or slow (40 to
TBD1MSPS).
Table 14. Output Format Control
Table 13. Output Mode Control
Value
Value
000
001
010
100
000
001
010
100
Two’s Complement
Output Format
Output Mode
Offset Binary
Gray Code
Pin Control
Pin Control
LVDS 2mA
LVDS 3mA
0x93[7:5]
0x93[2:0]
LVCMOS
ing. A static word can be placed on the output bus,
or two different words can alternate. In the alternate
mode, the values defined as Word 1 and Word 2 (as
shown in Table 15) are set on the output bus on alter-
nating clock phases.
Address 0xC0: test_io
Bits 7:6 User Test Mode
The four LSBs in this register (Output Test Mode) deter-
mine the test pattern in combination with registers
0xC2 through 0xC5. Refer to Table 16.
Address 0xC2: user_patt1_lsb
Address 0xC3: user_patt1_msb
These registers define the lower and upper eight bits,
respectively, of the first user-defined test word.
Address 0xC2: user_patt2_lsb
Address 0xC3: user_patt2_msb
These registers define the lower and upper eight bits,
respectively, of the second user-defined test word.
Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
These bits set the test mode to static (0x00) or
alternate (0x01) mode. Other values are re-
served.
Output Test Mode
Negative Full-Scale
Positive Full-Scale
Table 15. Output Test Modes
Checkerboard
User Pattern
0xC0[3:0]
One/Zero
Midscale
Reserved
Reserved
Off
user_patt1
0xAAAA
Word 1
0x8000
0x0000
0xFFFF
0xFFFF
N/A
N/A
user_patt2
Word 2
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0x5555
0x0000
N/A
N/A
N/A
N/A
N/A