pcm16c00 National Semiconductor Corporation, pcm16c00 Datasheet
pcm16c00
Related parts for pcm16c00
pcm16c00 Summary of contents
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... Na- tional DP83902A ST-NIC Ethernet Controller as one of the functions The PCM16C00 is fully compliant with PCMCIA version 2 1 and is compatible with serial 4-kbit and 16-kbit EEPROMs with 8-bit and 16-bit organizations that use the MICROW- ...
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... I O Memory Addressing Common Memory Addressing 5 2 Registers PCMCIA Registers PCM16C00 Specific Registers Standard Mode Register Set LAN (National ST-NIC) Mode Register Set 5 3 Logic Descriptions Card Interface Logic for PCMCIA Host I O Accesses ...
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... Connection Diagram Order Number PCM16C00VNG See NSC Package Number VNG144A 11669 – 2 ...
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... PCMCIA Host uses this pin to write memory space CMOS 6 mA Interrupt Request signal to PCMCIA Host CMOS 6 mA This pin allows the PCM16C00 to insert wait states in a PCMCIA transaction CMOS 6 mA Low indicates this I O access to the card is capable of 16-bit access Function 0 and 1 may use their IOCS16(1 0) ...
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... In LAN Mode these signals are assigned specific meaning for use with an Ethernet LAN IC Chip select for external attribute memory not shadowed in PCM16C00 IC Input Audio Signal Ring Indicator for function 0 In LAN Mode this is a packet indicator input Ring Indicator for function 1 ...
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... Register l 100k to V Port Write from LAN Device Register CC Write Acknowledge from the PCM16C00 signaling to the LAN that the PCMCIA Host has placed data in the entire I O Register This will insure that inputs do not float during a TABLE 3-4 Miscellaneous Pins Internal ...
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Pinout Description (Continued) Pin Total Host-Side Interface Pins 46 EEPROM Interface Pins 6 Card-Side Interface Pins 75 Miscellaneous Pins 17 Total Pins 144 4 0 Block Diagram FIGURE 4 11669 – 3 ...
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... Attribute Memory Addressing The Attribute Memory space contains both the Card Infor- mation Structure (CIS) PCMCIA Registers for both func- tions and PCM16C00 implementation specific registers Note that PCMCIA specifies that Attribute memory may only be accessed on even address byte boundaries The Attri- ...
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... HADDR(25 16) lines from the PCMCIA socket as appropriate even though these signals do not go into the PCM16C00 These signals can be considered to be side- band to the PCM16C00 The card design is free to use ex- ternal decoding logic for common memory For an Ethernet LAN card that desires to have a FLASH ...
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... CWAIT1 CWAIT0 When this bit is set to one (1) the PCM16C00 interprets this input signal active when it is low (0) When this bit is set to zero (0) the PCM16C00 interprets this input signal as active when it is high (1) The default bit value is zero ( the CWAIT( ) input signal is asserted ...
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... LDATA( ) bus and will use ADS to strobe the address phase on this bus to the LADDR( ) bus In this case the PCM16C00 will drive the LADDR( ) bus and latch the LDATA( ) bus to the LADDR( ) bus on an ADS strobe This bit should be set to a zero (0) when a bus ...
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... PCM16C00 will only pass I O transactions whose address falls within the I O window specified by the base and limit pair If this is set to a zero (0) the PCM16C00 will not test transactions’ addresses against the base and limit pair for that function and will therefore pass all I O transactions to ...
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... Note For consistency the PCM16C00 will alias all IntrReset bits on a write to insure that both functions operate in the same mode Also the Intr bits are aliased on writes as an indicator to the PCM16C00 that inter- ...
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... Data I O Register (Low and High Byte function 0 base This PCM16C00 register is 16 bits and is located in the I O address space The low byte of the Data I O Register is located Address offset 0x10h above function 0’s base address as given by the Function Base Address Regis- ter 0 The high byte is located Address offset 0x11h above function 0’ ...
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... Functional Description FIGURE 5-2 PCM16C00 and DP83902A Connection Schematic Note The FCLK(0) connection requires that MCLK(0) frequency is within the operating range of the DP83902A (typically 20 MHz) This schematic assumes that two 32k x 8 SRAMs are organized as shown to form a word-wide ring buffer and a 16-bit memory organization For detailed pin descriptions refer to the NSC ...
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... Data I O Register the PRQ remains low and WAIT states are generated to extend the PCMCIA bus cycle With PRQ asserted and the host trying to read the Data I O Register the PCM16C00 supplies the data to the host Once both bytes are read by the host the PCM16C00 ...
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... CIOWR HIOWR EEPROM INTERFACE NOTE The initial version of the PCM16C00 operates in both read and write modes with the 16k bit EEPROM only The PCM16C00 reads but cannot write the 4k bit EEPROM This is due to a subtle difference in the WRITE operation for ...
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... This leaves the lower 496 bytes in the EEPROM protected from overwrite The method for initializing the EEPROM using the PCM16C00 is to write the CIS and other protected data ( Ethernet node ID) to the PCM16C00 attribute memory SRAM and the PCM16C00 Specific Registers (at offsets ...
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... A value the highest priority the value 0 is the lowest In addition to this there is also a programmable 8-bit latency timer to guarantee a certain bus ownership time in clocks If the value is 0 the PCM16C00 arbiter will follow the priority policy strictly Here a higher priority unit may pre- empt a lower priority unit by removing its BACK ...
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... LAN device the PCM16C00 will pass the 8-bit transaction since the LAN IC register access is 8 bits With the common memory device the PCM16C00 will check the Memls8 bit in the Pin Polarity Register If Memls8 is clear (16-bit memory) the PCM16C00 will strobe MEMWEL ...
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... FCSRs on the PCM16C00 In either case system software is responsi- ble for writing a zero (0) to one of the PCM16C00’s Intr bits in an FCSR once interrupt processing is done if the PCM16C00 is using enhanced interrupts (IntrReset is set to ...
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Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage ( Input Current ( ...
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DC Electrical Characteristics Symbol Parameter I Maximum Output OZ Leakage Current Std TRI-STATE outputs I OZH L TRI-STATE output w 10k pull-up I OZH I OZL I Maximum I O OZT Leakage Current Std OZHT I OZLT ...
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FIGURE 1 Attribute Memory Read Timing 11669 – 5 ...
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Attribute Memory Read Timing Specifications (See Figure 1 ) Symbol Path tcR Read Cycle Time ta(A) Address Access Time ta(CE) CE1 Access Time ta(OE) Output Enable Access Time tdis(OE) Output Disable Time from HOE tdis(CE) Output Disable Time from CE1 ...
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FIGURE 2 Attribute Memory Write Cycle 11669 – 6 ...
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Attribute Memory Write Cycle Specifications (See Figure 2 ) Symbol Path tcW Write Cycle Time tw(WE) Write Enable Pulse Width tsu(A) HADDR Setup Time to HWE Falling tsu(D-WEH) HDATA Setup Time to HWE Rising th(D) HDATA Hold Time from HWE ...
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FIGURE 3 Common Memory Read Timing 11669 – 7 ...
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Common Memory Read Timing Specifications (See Figure 3 ) Symbol Path tcR Read Cycle Time ten(CE) Output Enable from CE Falling ten(OE) Output Enable from HOE Falling tsu(A) HADDR Setup Time to HOE Falling th(A) HADDR Hold Time from HOE ...
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FIGURE 4 Common Memory Write Timing 11669 – 8 ...
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Common Memory Write Timing Specifications (See Figure 4 ) Symbol Path tcW Write Cycle Time tw(WE) HWE Pulse Width tsu(A) HADDR Setup Time from HWE Falling tsu(D-WEH) HDATA Setup Time from HWE Rising th(D) HDATA Hold Time from HWE Rising ...
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FIGURE Read Timing Specification 11669 – 9 ...
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I O Read Timing Specifications (See Figure 5 ) Symbol Path tsu REG(IORD) REG Setup to HIORD Falling tsu CE(IORD) CE Setup to HIORD Falling tsu A(IORD) HADDR Setup to HIORD Falling tw (IORD) HIORD Pulse Width tdf INPACK(IORD) INPACK ...
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FIGURE Write Timing Specification 11669 – 10 ...
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I O Write Timing Specifications (See Figure 6 ) Symbol Path tsu REG(IOWR) REG Setup to HIOWR Falling tsu CE(IOWR) CE Setup to HIOWR Falling tsu A(IOWR) HADDR Setup to HIOWR Falling tsu(IOWR) HDATA Setup to HIOWR Falling tw(IOWR) HIOWR ...
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FIGURE 7 Bus Arbitration Timing 11669 – 11 ...
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Bus Arbitration Timing Specifications (See Figure 7 ) Symbol Path tv(LA-ADS) LADDR Valid from ADS td(LA-HA) LADDR Delay from HADDR td(LA-LD) LADDR Delay from LDATA tckq(BACK) BACK Delay from MCLK(0) Falling td(WE-MWR) MEMWEH Delay from MEMWR td(WE-MWR) MEMWEL Delay from ...
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... PCM16C00 IC Specific Timing Specifications Symbol Path td(CS) CS(0) CS(1) from Valid Address td(IREQ) IREQ Delay from CINT td(SPKR) SPKR Delay from SPK IN td(PORT) DPORT Delay from HWE td(SRESET) SRESET(1 0) Delay from RESET td(PCNTL) PCNTL(0) Delay from HWE td(FCLK) FCLK(1 0) Delay from MCLK(1 0) Frequency MCLK(1 0) ...
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Physical Dimensions millimeters 144-Lead (20mm x 20mm) Molded Thin Plastic Quad Flat Package (JEDEC) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE ...