pcm16c00 National Semiconductor Corporation, pcm16c00 Datasheet - Page 4

• Manufacturer Part Number: pcm16c00
• Description: Configurable Multiple Function Pcmcia Interface Chip
• Manufacturer: National Semiconductor Corporation

HDATA(15 0)
HADDR(15 0)
HOE
HWE
HIORD
HIOWR
IREQ
HWAIT
IOIS16
INPACK
CE1
CE2
REG
RESET
SPKR
STSCHG
3 0 Pinout Description
Name
Pin
Type
Pin
I O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
107 74 – 72
89 98 100
90 93 94
96 95 88
87 85 – 80
76 78 79
112 – 109
102 – 106
No
115
116
101
114
Pin
99
92
91
66
75
67
68
65
70
71
Compatibility
TTL 6 mA
TTL
TTL
TTL
TTL
TTL
CMOS 6 mA
CMOS 6 mA
CMOS 6 mA
CMOS 6 mA
TTL
TTL
TTL
TTL Schmitt
CMOS 6 mA
CMOS 6 mA
TABLE 3-1 PCMCIA Host-Side Pins
Level
l
l
l
l
l
l
l
l
l
l
4
100k to GND
100k to GND
100k to V
100k to V
100k to V
100k to V
100k to V
100k to V
100k to V
100k to V
Resistor
Internal
CC
CC
CC
CC
CC
CC
CC
CC
PCMCIA Host Data Bus
PCMCIA Host Address Bus
PCMCIA Host uses this pin to read common or
attribute memory space
PCMCIA Host uses this pin to write common or
attribute memory space
PCMCIA Host uses this pin to read I O memory
space
PCMCIA Host uses this pin to write I O
memory space
Interrupt Request signal to PCMCIA Host
This pin allows the PCM16C00 to insert wait
states in a PCMCIA transaction
Low indicates this I O access to the card is
capable of 16-bit access Function 0 and 1 may
use their IOCS16(1 0)
this signal and inform the host if a 16-bit access
to the target is feasible
Signals a valid I O read
Indicates even address byte Odd addresses
are not released CE1
encodings are specified by the PCMCIA
Specification
Indicates odd addressing only CE1
CE2
PCMCIA Specification
Indicates access to attribute memory space or
I O address space REG
access common memory space
Asynchronously resets the PCM16C00
If Audio bits are set in the Card Configuration
Status Register and in either of the Function
Configuration Status Registers 0 1 then
SPKR
high
STSCHG
and SigChg bit are set in the Card
Configuration Status Register
assertion encodings are specified by the
is invert of SPK IN pin else SPKR
is asserted when the Changed bit
Description
respectively to control
and CE2
must be high to
assertion
and
is