pcm16c00 National Semiconductor Corporation, pcm16c00 Datasheet - Page 5

• Manufacturer Part Number: pcm16c00
• Description: Configurable Multiple Function Pcmcia Interface Chip
• Manufacturer: National Semiconductor Corporation

LDATA(15 0)
DPORT(3 0)
EARD
SPK IN
RI IN(0)
RI IN(1)
CIORD
CIOWR
CWAIT(1 0)
CS(1 0)
BHE
READY(1 0)
CINT(1 0)
SRESET(1 0)
EEDO
EEDI
EECS
EESK
EESize
EEORG
3 0 Pinout Description
Name
Note The Enable EEPROM function is performed in software by writing to the EEPROM Control Register The Enable EEPROM bit will default to low (disabled)
upon power on
Pin
Name
Pin
Type
Pin
O
O
O
I
I
I
Type
Pin
I O
I O
O
O
O
O
O
O
I
I
I
I
I
I
No
119
120
122
121
117
118
Pin
144 – 141
140 64
139 63
136 60
138 62
137 61
20 19
18 17
13 – 7
5 – 1
No
128
127
129
Pin
53
23
22
21
Compatibility
TTL
CMOS 6 mA
CMOS 6 mA
CMOS 6 mA
TTL
TTL
Level
Compatibility
TTL 6 mA
TTL 6 mA
CMOS 6 mA
TTL Schmitt
TTL Schmitt
TTL Schmitt
CMOS 6 mA
CMOS 6 mA
TTL
CMOS 6 mA
CMOS 6 mA
TTL
TTL Schmitt
CMOS 6 mA
(Continued)
Level
TABLE 3-2 Serial EEPROM Interface Pins
TABLE 3-3 Card-Side Interface Pins
l
l
100k to V
100k to V
Resistor
Internal
Hold Circuit
(Note 1)
l
100k to V
Resistor
Internal
CC
CC
5
Serial Data in from EEPROM
Serial Data out to EEPROM
EEPROM Chip Select
EEPROM Clock Freq
EEPROM Size If high the EEPROM size is 16-kbit else the
size is 4-kbit
EEPROM Organization pin If high the EEPROM is organized
as 16-bit words else organization is 8 bits
CC
Card-side Data Bus
Generic Direction programmable function port for
additional user signals In LAN Mode these signals are
assigned specific meaning for use with an Ethernet LAN
IC
Chip select for external attribute memory not shadowed
in PCM16C00 IC
Input Audio Signal
Ring Indicator for function 0 In LAN Mode this is a
packet indicator input
Ring Indicator for function 1
I O read signals are passed through from HIORD
according to the expression shown below when a valid
address is decoded
(CIORD
I O write signals are passed through from HIOWR
according to the expression shown below when a valid
address is decoded
CIOWR
Card-side transaction wait state inputs
Chip select for each function
Byte high enable When de-asserted and CS( )
asserted an 8-bit access on LDATA(7 0) is in progress
This holds for both odd and even addresses When
asserted and CS( )
LDATA(15 0) is in progress
Indicates that the function is either READY or E READY
(i e - Busy) This signal is used to assert the Rdy Bsy
bit in Pin Replacement Registers
Card-side interrupt input signals
Signals reset to Card-side functions
e
e
HIOWR
HIORD
e
Description
MCLK(0) 32
asserted a 16-bit access on
Description
a
a
REG
REG
a
a
(CE1
(CE1
CE2 )
CE2 )