CY28325PVC-2 Cypress Semiconductor Corp., CY28325PVC-2 Datasheet
CY28325PVC-2
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CY28325PVC-2 Summary of contents
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Features • Spread Spectrum Frequency Timing Generator for VIA Pentiumâ 4 Chipsets • Programmable clock output frequency with less than 1 MHz increment • Integrated fail-safe Watchdog Timer for system recovery • Automatically switch to hardware-selected or software- programmed clock ...
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Pin Definitions Pin Name Pin No REF/FS4 1 CPUT_0:1 40, 39, 35, 34 CPUC_0:1 CPUT_CS_F 42, 41 CPUC_CS_F APIC0:1 46, 45 AGP 0:2 23, 26, 27 PCI_F/FS0 10 PCI1/FS1 11 PCI2/MULTSEL 12 1 PCI3:8 14, 15, ...
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Pin Definitions (continued) Pin Name Pin No. VTT_PWRGD# 33 VDD_CPU_CS, 43, 48 VDD_APIC VDD_REF 16, 24, 38 VDD_48MHz, VDD _PCI, VDD_AGP, VDD_CPU GND_REF 3, 9, 13, 20, 25, 36, 44, 47 GND_48MHz, GND_PCI, GND_AGP, GND_CPU, GND_APIC Swing Select ...
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Swing Select Functions (continued) Board Target MultSEL1 MultSEL0 Trace/Term Serial Data Interface To ...
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Table 2. Block Read and Block Write Protocol Block Write Protocol Bit Description 1 Start 2:8 Slave address – 7 bits 9 Write 10 Acknowledge from slave Command Code – 8 bits 11:18 “00000000” stands for block operation 19 Acknowledge ...
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Data Byte Configuration Map Data Byte 0 Bit Pin# Name Bit 7 – Reserved Bit 6 – SEL2 Bit 5 – SEL1 Bit 4 – SEL0 Bit 3 – FS_Override Bit 2 – SEL4 Bit 1 – SEL3 Bit 0 ...
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Data Byte 3 Bit Pin# Name Bit 7 – Reserved Bit 6 8 SEL_48MHZ Bit 5 7 48MHz Bit 4 8 24_48MHz Bit 3 10 PCI_F Bit 2 27 AGP2 Bit 1 26 AGP1 Bit 0 23 AGP0 Data Byte ...
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Data Byte 6 Bit Pin# Name Bit 7 – Reserved Bit 6 – Reserved Bit 5 – Reserved Bit 4 – Reserved Bit 3 – Reserved Bit 2 – Reserved Bit 1 – Reserved Bit 0 – Reserved Data Byte ...
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Data Byte 9 (continued) Bit Pin# Name Bit 3 – RST_EN_FC Bit 2 – WD_TO_STAT US Bit 1 – WD_EN Bit 0 – Reserved Data Byte 10 Bit Pin# Name Bit 7 – CPU_CS_F Skew2 Bit 6 – CPU_CS_F Skew1 ...
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Data Byte 11 Bit Pin# Name Bit 7 – ROCV_FREQ_N7 Bit 6 – ROCV_FREQ_N6 Bit 5 – ROCV_FREQ_N5 Bit 4 – ROCV_FREQ_N4 Bit 3 – ROCV_FREQ_N3 Bit 2 – ROCV_FREQ_N2 Bit 1 – ROCV_FREQ_N1 Bit 0 – ROCV_FREQ_N0 Data Byte ...
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Data Byte 14 (continued) Bit Pin# Name Bit 6 – CPU_FSEL_M6 Bit 5 – CPU_FSEL_M5 Bit 4 – CPU_FSEL_M4 Bit 3 – CPU_FSEL_M3 Bit 2 – CPU_FSEL_M2 Bit 1 – CPU_FSEL_M1 Bit 0 – CPU_FSEL_M0 Data Byte 15 Bit Pin# ...
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Table 4. Frequency Selection Table Input Conditions FS4 FS3 FS2 FS1 SEL4 SEL3 SEL2 SEL1 ...
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Register Summary Name Pro_Freq_EN Programmable output frequencies enabled 0 = Disabled (default Enabled. When it is disabled, the operating output frequency will be determined by either the latched value of FS[4:0] inputs or the programmed value of SEL[4:0]. ...
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Program the CPU output frequency When the programmable output frequency feature is enabled (Pro_Freq_EN bit is set), the CPU output frequency is deter- mined by the following equation: Fcpu = G * (N+3)/(M+3). “N” and “M” are the values programmed ...
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Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Supply Voltage ................................................. –0.5 to +7.0V Input Voltage ..............................................–0. Operating Conditions Over which Electrical Parameters are Guaranteed Parameter ...
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Switching Characteristics Parameter Output t 24_48 MHz, 48 Output Duty Cycle 1 MHz, REF, AGP, PCI t CPU_CS Output Duty Cycle 1 t 24_48 MHz Rising Edge Rate 2 t PCI, AGP Rising Edge Rate 2 t 24_48 ...
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Switching Waveforms Duty Cycle Timing (Single-ended Output Duty Cycle Timing (CPU Differential Output All Outputs Rise/Fall Time OUTPUT t 2 CPU-CPU Clock Skew Host_b Host Host_b Host t 4 AGP-AGP Clock Skew ...
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PRELIMINARY Switching Waveforms (continued) CPU Clock Cycle-Cycle Jitter Host_b Host Cycle-Cycle Clock Jitter CLK Ordering Information Ordering Code Package Name CY28325-2 PVC Package Diagram Pentium registered trademark of Intel Corporation. VIA is a trademark of VIA Technologies, ...
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Document Title: CY28325-2 FTG for Via Pentium 4â Chipsets Document Number: 38-07119 REV. ECN NO. Issue Date ** 111733 03/06/02 *A 122790 12/27/02 Document #: 38-07119 Rev. *A PRELIMINARY Orig. of Change IKA New Data Sheet Added notes to page ...