W230H Cypress Semiconductor Corp., W230H Datasheet
W230H
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W230H Summary of contents
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Features • Maximized EMI Suppression using Cypress’s Spread Spectrum technology • Single-chip system frequency synthesizer for VIA K7 chipset • Two copies of CPU output • Six copies of PCI output • One 48-MHz output for USB • One 24-MHz ...
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Pin Definitions Pin Name Pin No. Pin Type CPUT0, 43, 44, 46 CPUC0, (open- CPUT_CS drain) PCI2:5 10, 11, 12, 13 PCI1/FS1 8 I/O PCI0/MODE 7 I/O PWRDWN# 41 48MHz/FS2 26 I/O 24_48MHz/ 25 I/O FS3 REF1/FS0 48 I/O REF0/ ...
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Overview The W230 was developed as a single-chip device to meet the clocking needs of VIA K7 core logic chip sets. In addition to the typical outputs provided by a standard FTG, the W230 adds a thirteenth output buffer, supporting ...
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Spread Spectrum Frequency Timing Generator The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the am- plitudes of the radiated electromagnetic ...
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Serial Data Interface The W230 features a two-pin, serial data interface that can be used to configure internal register settings that control partic- ular device functions. Upon power-up, the W230 initializes with default register settings, therefore the use of this ...
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Writing Data Bytes Each bit in the data bytes controls a particular device function except for the “reserved” bits, which must be written as a logic 0. Bits are written MSB (most significant bit) first, which is bit Table 5. ...
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Table 5. Data Bytes 0–7 Serial Configuration Map (continued) Affected Pin Bit(s) Pin No. Pin Name 1 32, 31, SDRAM4:7 29 38, 37, SDRAM0:3 35, 34 Data Byte ...
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Table 6. Additional Frequency Selections through Serial Data Interface Data Bytes Input Conditions Data Byte 0, Bit Bit 2 Bit 1 Bit 6 SEL_4 SEL_3 SEL_2 ...
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Absolute Maximum Ratings Stresses greater than those listed in this table may cause per- manent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions . Parameter ...
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DC Electrical Characteristics: Parameter Description Crystal Oscillator V X1 Input Threshold Voltage TH C Load Capacitance, Imposed on LOAD [6] External Crystal C X1 Input Capacitance IN,X1 Pin Capacitance/Inductance C Input Pin Capacitance IN C Output Pin Capacitance OUT L ...
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PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF Parameter Description t Period P t High Time H t Low Time L t Output Rise Edge Rate R t Output Fall Edge Rate F t Duty Cycle D ...
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Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description f Frequency, Actual f Deviation from 24 MHz D m/n PLL Ratio t Output Rise Edge Rate R t Output Fall Edge Rate F t Duty Cycle D ...
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Layout Diagram +3.3V Supply FB 0.005 Dale ILB1206 - 300 (300 @ 100 MHz) C1, C3 & 10– VIA to GND plane layer Note: Each supply plane or ...
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Package Diagram 48-Pin Small Shrink Outline Package (SSOP, 300 mils) Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102 Document #: 38-07224 Rev. *A © Cypress Semiconductor Corporation, 2001. The information ...
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Document Title:W230 Spread Spectrum FTG for VIA K7 Chipset Document Number: 38-07224 Issue REV. ECN NO. Date ** 110489 10/21/01 *A 122841 12/21/02 Document #: 38-07224 Rev. *A Orig. of Change Description of Change SZV Change from Spec number: 38-00890 ...