W163 Cypress Semiconductor Corp., W163 Datasheet
W163
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W163 Summary of contents
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... Cycle-to-Cycle Jitter: ..................................................200 ps Output-to-Output Skew: ..............................................250 ps Device-to-Device Skew: ..............................................700 ps Propagation Delay:......................................................350 ps Pin Configuration REF Q0 QFB Q1 Q0 GND • 3901 North First Street • San Jose W163 < 133 MHz OUT SOIC 1 8 QFB VDD • CA 95134 • ...
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... VDD 6 GND 4 Overview The W163 products are five-output zero delay buffers. A Phase-Locked Loop (PLL) is used to take a time-varying signal and provide five copies of that same signal out. The internal feedback to the PLL provides outputs in phase with the refer- ence inputs. Spread Aware Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation ...
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... Min Typ Max 40 0.8 2.0 0.4 2.4 50 100 Min Typ Max 10 133 10 133 2.5 1.5 2.5 1 –350 0 350 –250 0 250 –700 0 700 1.0 200 to 1.4V. W163 V °C °C °C W Unit Unit MHz MHz Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Option Name -05, -15 G 8-pin Plastic SOIC (150-mil) W163 Package Type Page ...
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... Document Title: W163 Spread Aware™, Zero Delay Buffer Document Number: 38-07149 Issue REV. ECN NO. Date ** 110258 12/15/01 Document #: 38-07149 Rev. ** Orig. of Change SZV Change from Spec number: 38-00787 to 38-07149 Description of Change W163 Page ...