MC88915T Motorola Semiconductor Products, MC88915T Datasheet - Page 18

• Manufacturer Part Number: MC88915T
• Description: Low Skew CMOS PLL Clock Driver
• Manufacturer: Motorola Semiconductor Products

1. Figure 6 shows a loop filter and analog isolation scheme
1a.All loop filter and analog isolation components should be
1b.The 47
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which will be effective in most applications. The following
guidelines should be followed to ensure stable and
jitter–free operation:
tied as close to the package as possible. Stray current
passing through the parasitics of long traces can cause
undesirable voltage transients at the RC1 pin.
capacitor, and the 0.1 F high frequency bypass capacitor
form a wide bandwidth filter that will minimize the 88915T’s
sensitivity to voltage transients from the system digital V
supply and ground planes. This filter will typically ensure
that a 100mV step deviation on the digital V
cause no more than a 100pS phase deviation on the
88915T outputs. A 250mV step deviation on V
recommended filter values should cause no more than a
250pS phase deviation; if a 25 F bypass capacitor is used
(instead of 10 F) a 250mV V
than a 100pS phase deviation.
If good bypass techniques are used on a board design
near components which may cause digital V
noise, the above described V
occur at the 88915T’s digital V
the bypass filtering scheme shown in Figure 6 is to give the
resistors, the 10 F low frequency bypass
Figure 6. Recommended Loop Filter and Analog Isolation Scheme for the MC88915T
CC
CC
Notes Concerning Loop Filter and Board Layout Issues
CC
step should cause no more
step deviations should not
supply. The purpose of
CC
CC
CC
and ground
supply will
using the
CC
1c.There are no special requirements set forth for the loop
1d.The 1M reference resistor injects current into the internal
2. In addition to the bypass capacitors used in the analog filter
88915T additional protection from the power supply and
ground plane transients that can occur in a high frequency,
high speed digital system.
filter resistors (1M
(0.1 F) can be a ceramic chip capacitior, the same as a
standard bypass capacitor.
charge pump of the PLL, causing a fixed offset between
the outputs and the SYNC input. This also prevents
excessive jitter caused by inherent PLL dead–band. If the
VCO (2X_Q output) is running above 40MHz, the 1M
resistor provides the correct amount of current injection
into the charge pump (2–3 A). For the TFN55, 70 or 100,
if the VCO is running below 40MHz, a 1.5M
resistor should be used (instead of 1M ).
of Figure 6, there should be a 0.1 F bypass capacitor
between each of the other (digital) four V
board ground plane. This will reduce output switching
noise caused by the 88915T outputs, in addition to
reducing potential for noise in the ‘analog’ section of the
chip. These bypass capacitors should also be tied as close
to the 88915T package as possible.
and 330 ). The loop filter capacitor
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MOTOROLA
pins and the
reference