adv7188 Analog Devices, Inc., adv7188 Datasheet - Page 102

• Manufacturer Part Number: adv7188
• Description: Multiformat Sdtv Video Decoder With Fast Switch Overlay Support
• Manufacturer: Analog Devices, Inc.

ADV7188
Address Register
0x45
0x46
0x47
0x48
0x49
Raw Status 2 (Read Only)
Interrupt Status 2
(Read Only)
Interrupt Clear 2
(Write Only)
Interrupt Mask 2
(Read/Write)
Raw Status 3
(Read Only)
Bit Description
CCAPD.
Reserved.
EVEN_FIELD.
Reserved.
MPU_STIM_INTRQ.
CCAPD_Q.
GEMD_Q.
Reserved.
SD_FIELD_CHNGD_Q.
Reserved.
Reserved.
MPU_STIM_INTRQ_Q.
CCAPD_CLR.
GEMD_CLR.
Reserved.
SD_FIELD_CHNGD_CLR.
Reserved.
Reserved.
MPU_STIM_INTRQ_CLR.
CCAPD_MSKB.
GEMD_MSKB.
CGMS_MSKB.
SD_FIELD_CHNGD_MSKB.
Reserved.
MPU_STIM_INTRQ_MSKB.
SD_OP_50Hz. This bit indicates if the
SD 60 Hz or SD 50 Hz frame rate is at output.
SD_V_LOCK.
SD_H_LOCK.
Reserved.
SCM_LOCK.
Reserved.
Reserved.
Reserved.
Rev. A | Page 102 of 112
0
1
0
1
0
1
0
1
7 6 5 4 3 2 1 0
x
x x
x
x
0 0
x
x
x
x
0
1
0
1
0
1
0
1
0
1
Bit
x x x
x x
0 0
0 0
x
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CCAPD data detected.
Closed captioning not detected in
the input video signal.
Closed caption data detected in the
video input signal.
SD signal has not changed the field
from odd to even or vice versa.
SD signal has changed the field from
odd to even or vice versa.
Clears CCAPD_Q bit.
Does not clear.
Clears SD_FIELD_CHNGD_Q bit.
Clears MPU_STIM_INTRQ_Q bit.
Masks CCAPD_Q bit.
Unmasks CCAPD_Q bit.
Masks GEMD_Q bit.
Masks SD_FIELD_CHNGD_Q bit.
Not used.
Masks MPU_STIM_INTRQ_Q bit.
SD 60 Hz signal output.
SD 50 Hz signal output.
SD horizontal sync lock established.
SECAM lock established.
Comments
No CCAPD data detected.
Current SD field is odd numbered.
Current SD field is even numbered.
MPU_STIM_INT = 0.
MPU_STIM_INT = 1.
Gemstar data not detected in the
input video signal.
Gemstar data detected in the input
video signal.
Not used.
Not used.
Manual interrupt not set.
Manual interrupt set.
Does not clear.
Clears GEMD_Q bit.
Does not Clear.
Not used.
Not used.
Does not clear.
Unmasks GEMD_Q bit.
Masks CGMS_CHNGD_Q bit.
Unmasks SD_FIELD_CHNGD_Q bit.
Unmasks MPU_STIM_INTRQ_Q bit.
SD vertical sync lock not established.
SD vertical sync lock established.
SD horizontal sync lock not
established.
Not used.
SECAM lock not established.
Not used.
Not used.
Not used.
Notes
These bits are status bits only.
They cannot be cleared or
masked. Register 0x46 is used
for this purpose.
These bits can be cleared or
masked by Registers 0x47 and
0x48, respectively.
Note that interrupt in
Register 0x46 for the CC,
Gemstar, CGMS, and WSS data
is using the Mode 1 data
slicer.
Note that interrupt in
Register 0x46 for the CC,
Gemstar, CGMS, and WSS data
is using the Mode 1 data
slicer.
Note that interrupt in
Register 0x46 for the CC,
Gemstar, CGMS, and WSS data
is using the Mode 1 data
slicer.
These bits are status bits only.
They cannot be cleared or
masked. Register 0x4A is used
for this purpose.