adv7718 Analog Devices, Inc., adv7718 Datasheet
adv7718
Related parts for adv7718
adv7718 Summary of contents
Page 1
V AA ADV7177/ADV7178 ADV7177 ONLY OSD_EN OSD_0 OSD_1 OSD_2 8 COLOR 4:2:2 TO DATA YCrCb 4:4 INTER- P7–P0 YUV POLATOR MATRIX 8 P15–P8 HSYNC VIDEO TIMING FIELD/VSYNC GENERATOR BLANK CLOCK CLOCK CLOCK/2 Protected by U.S. Patent Numbers ...
Page 2
ADV7177/ADV7178–SPECIFICATIONS 5 V SPECIFICATIONS ( Parameter 3 STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity 3 DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL 4 Input Current, I ...
Page 3
V SPECIFICATIONS (V AA Parameter 3 STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL 3, 4 Input Current Input ...
Page 4
ADV7177/ADV7178–SPECIFICATIONS 5 V DYNAMIC SPECIFICATIONS Parameter FILTER CHARACTERISTICS 3 Luma Bandwidth (Low-Pass Filter) Stopband Cutoff Passband Cutoff Chroma Bandwidth Stopband Cutoff Passband Cutoff Luma Bandwidth (Low-Pass Filter) Stopband Cutoff Passband Cutoff F 3 ...
Page 5
V DYNAMIC SPECIFICATIONS Parameter FILTER CHARACTERISTICS 3 Luma Bandwidth (Low-Pass Filter) Stopband Cutoff Passband Cutoff Chroma Bandwidth Stopband Cutoff Passband Cutoff Luma Bandwidth (Low-Pass Filter) Stopband Cutoff Passband Cutoff ...
Page 6
ADV7177/ADV7178 5 V TIMING SPECIFICATIONS Parameter 3, 4 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth SCLOCK Low Pulsewidth Hold Time (Start Condition Setup Time (Start Condition Data Setup Time SDATA, ...
Page 7
V TIMING SPECIFICATIONS Parameter 3, 4 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth SCLOCK Low Pulsewidth Hold Time (Start Condition Setup Time (Start Condition Data Setup Time SDATA, SCLOCK ...
Page 8
ADV7177/ADV7178 SDATA SCLOCK CLOCK HSYNC, CONTROL FIELD/VSYNC, I/PS BLANK PIXEL INPUT DATA HSYNC, CONTROL FIELD/VSYNC, O/PS BLANK CLOCK CLOCK/2 CLOCK CLOCK/2 CLOCK OSD EN OSD0– ...
Page 9
ABSOLUTE MAXIMUM RATINGS V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 10
ADV7177/ADV7178 Input/ Pin Number Mnemonic Output 1, 20, 28 CLOCK/2 O 3–10, 12–14, P15–P0 I 37–41 11 OSD_EN I HSYNC 15 I/O 16 FIELD/VSYNC I/O BLANK 17 I/O 18 ALSB I 19, 21, 29, 42 ...
Page 11
Typical Performance Characteristics – 0 –10 TYPE A –20 –30 –40 –50 TYPE B – FREQUENCY – MHz 0 –10 –20 –30 –40 –50 – FREQUENCY – MHz ...
Page 12
ADV7177/ADV7178 0 –10 –20 –30 –40 –50 – FREQUENCY – MHz DATA PATH DESCRIPTION For PAL and NTSC M, N modes, YCrCb 4:2:2 data is input via the CCIR-656 ...
Page 13
PIXEL TIMING DESCRIPTION The ADV7177/ADV7178 can operate in either 8-bit or 16-bit YCrCb Mode. 8-Bit YCrCb Mode This default mode accepts multiplexed YCrCb inputs through the P7–P0 pixel inputs. The inputs follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, ...
Page 14
ADV7177/ADV7178 Mode 0 (CCIR-656): Slave Option (Timing Register 0 TR0 = The ADV7177/ADV7178 is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel data. ...
Page 15
DISPLAY 622 623 624 625 EVEN FIELD ODD FIELD F DISPLAY 309 310 311 312 313 ODD FIELD EVEN FIELD ANALOG VIDEO VERTICAL BLANK VERTICAL ...
Page 16
ADV7177/ADV7178 Mode 1: Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = this mode the ADV7177/ADV7178 accepts horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when ...
Page 17
Mode 1: Master Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = this mode the ADV7177/ADV7178 can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when ...
Page 18
ADV7177/ADV7178 DISPLAY 622 623 624 625 HSYNC BLANK VSYNC EVEN FIELD DISPLAY 309 310 311 HSYNC BLANK VSYNC ODD FIELD Mode 2: Master Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = ...
Page 19
HSYNC VSYNC PAL = 12 NTSC = 16 BLANK PIXEL DATA Mode 3: Master/Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = ...
Page 20
ADV7177/ADV7178 DISPLAY 622 623 624 HSYNC BLANK EVEN FIELD FIELD DISPLAY 309 310 311 HSYNC BLANK ODD FIELD FIELD POWER-ON RESET After power-up necessary to execute a reset operation. A reset occurs on the falling edge of a ...
Page 21
To control the various devices on the bus, the following protocol must be followed: First, the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDATA while SCLOCK remains high. This indicates that ...
Page 22
ADV7177/ADV7178 REGISTER ACCESSES The MPU can write to or read from all of the ADV7177/ADV7178 registers except the subaddress register, which is a write-only regis- ter. The subaddress register determines which register the next read or write operation accesses. All ...
Page 23
MR07 OUTPUT SELECT MR06 0 YC OUTPUT 1 RGB/YUV OUTPUT MR07 ZERO SHOULD BE WRITTEN TO THIS BIT MR17 ONE SHOULD BE WRITTEN TO THIS BIT COLOR BAR CONTROL MR17 0 DISABLE 1 ENABLE Output Select (MR06) This bit specifies ...
Page 24
ADV7177/ADV7178 SUBCARRIER FREQUENCY REGISTER 3-0 (FSC3–FSC0) (Address [SR4–SR0] = 05H–02H) These 8-bit-wide registers are used to set up the subcarrier frequency. The value of these registers are calculated by using the following equation Subcarrier Frequency Register = F ...
Page 25
CLOSED CAPTIONING EVEN FIELD DATA REGISTER 1–0 (CED15–CED0) (Address [SR4–SR0] = 09–08H) These 8-bit-wide registers are used to set up the closed captioning extended data bytes on even fields. Figure 29 shows how the high and low bytes are set ...
Page 26
ADV7177/ADV7178 MR27 RGB/YUV CONTROL MR26 0 RGB OUTPUT 1 YUV OUTPUT LOW POWER MODE MR27 0 DISABLE 1 ENABLE MODE REGISTER 2 MR2 (MR27–MR20) (Address [SR4-SR0] = 0DH) Mode Register 8-bit-wide register. Figure 32 shows the various ...
Page 27
MR37 MR37 ZERO SHOULD BE WRITTEN TO THIS BIT INPUT DEFAULT COLOR MR36 0 1 OSD REG 0 OSD REG 1 OSD REG 2 OSD REG 11 OSD Enable (MR35) A logic one in MR35 will enable the OSD function ...
Page 28
ADV7177/ADV7178 BOARD DESIGN AND LAYOUT CONSIDERATIONS The ADV7177/ADV7178 is a highly integrated circuit containing both precision analog and high speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high ...
Page 29
OSD INPUTS 37–41, + 3–10, 12–14 AA PIXEL DATA 4k RESET 100nF “UNUSED INPUTS SHOULD BE GROUNDED” 33pF 27MHz XTAL 33pF 27MHz OR 13.5MHz CLOCK OUTPUT +5V (V POWER SUPPLY DECOUPLING FOR EACH POWER SUPPLY GROUP 0.1 F ...
Page 30
ADV7177/ADV7178 The ADV7177/ADV7178 supports closed captioning, conform- ing to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of even fields. ...
Page 31
NTSC WAVEFORMS (WITH PEDESTAL) 130.8 IRE 100 IRE 7.5 IRE 0 IRE –40 IRE 100 IRE 7.5 IRE 0 IRE –40 IRE 963.8mV 286mVp-p 650mV 335.2mV 0mV 100 IRE 7.5 IRE 0 IRE –40 IRE APPENDIX 3 PEAK COMPOSITE REF ...
Page 32
ADV7177/ADV7178 130.8 IRE 100 IRE 0 IRE –40 IRE 100 IRE 0 IRE –40 IRE 978mV 286mVp-p 650mV 299.3mV 0mV 100 IRE 0 IRE –40 IRE NTSC WAVEFORMS (WITHOUT PEDESTAL) 1289.8mV PEAK COMPOSITE REF WHITE 1052.2mV 714.2mV BLANK/BLACK LEVEL 338mV ...
Page 33
PAL WAVEFORMS PEAK COMPOSITE 696.4mV BLANK/BLACK LEVEL 696.4mV BLANK/BLACK LEVEL 672mVp-p 698.4mV BLANK/BLACK LEVEL ADV7177/ADV7178 REF WHITE SYNC LEVEL REF WHITE SYNC LEVEL PEAK CHROMA ...
Page 34
ADV7177/ADV7178 334mV 171mV BETACAM LEVEL 0mV 171mV 334mV 505mV 309mV 158mV BETACAM LEVEL 0mV –158mV –309mV –467mV 232mV 118mV SMPTE LEVEL 0mV –118mV –232mV –350mV UV WAVEFORMS 505mV BETACAM LEVEL 0mV 467mV BETACAM LEVEL 0mV 350mV SMPTE LEVEL 0mV 505mV ...
Page 35
The ADV7177/ADV7178 registers can be set depending on the user standard required. The following examples give the various register formats for several video standards. In each case the output is set to composite o/p with all DACs powered up and ...
Page 36
ADV7177/ADV7178 If an output filter is required for the CVBS, Y, UV, Chroma, and RGB outputs of the ADV7177/ADV7178, the following filter in Figure 56 can be used. Plots of the filter characteristics are shown in Figure 57. An output ...
Page 37
For external buffering of the ADV7177/ADV7178 DAC outputs, the configuration in Figure 58 is recommended. This configuration shows the DAC outputs running at half (18 mA) their full current (34.7 mA) capability. This will allow the ADV7177/ADV7178 to dissipate less ...
Page 38
ADV7177/ADV7178 Revision History Location Data Sheet changed from REV REV. B. Changed page 1 jump to page 9 instead of page 11 due to TPC change . . . . . . . . . . . . ...
Page 39
...
Page 40
...