adv7718 Analog Devices, Inc., adv7718 Datasheet - Page 17
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adv7718
Manufacturer Part Number
adv7718
Description
Integrated Digital Ccir-601 Pal/ntsc Video Encoder
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADV7718.pdf
(40 pages)
Mode 1: Master Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode the ADV7177/ADV7178 can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD
input when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is
disabled, the ADV7177/ADV7178 automatically blanks all normally blank lines. Pixel data is latched on the rising clock edge follow-
ing the timing signal transitions. Mode 1 is illustrated in Figure 11 (NTSC) and Figure 12 (PAL). Figure 13 illustrates the HSYNC,
BLANK and FIELD for an odd or even field transition relative to the pixel data.
Mode 2: Slave Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode the ADV7177/ADV7178 accepts horizontal and vertical SYNC signals. A coincident low transition of both HSYNC
and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even
field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7177/ADV7178 automatically blanks all nor-
mally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 14 (NTSC) and Figure 15 (PAL).
VSYNC
BLANK
VSYNC
BLANK
HSYNC
HSYNC
522
DISPLAY
DISPLAY
260
523
261
HSYNC
BLANK
FIELD
PIXEL
DATA
524
262
525
263
PAL = 12
NTSC = 16
1
264
CLOCK/2
EVEN FIELD
ODD FIELD
2
CLOCK/2
265
3
266
4
267
5
268
VERTICAL BLANK
VERTICAL BLANK
6
269
EVEN FIELD
ODD FIELD
7
270
8
271
9
PAL = 132
NTSC = 122
272
10
273
CLOCK/2
Cb
CLOCK/2
11
ADV7177/ADV7178
274
Y
Cr
Y
20
283
21
DISPLAY
284
DISPLAY
22
285