epm3064a Altera Corporation, epm3064a Datasheet - Page 16

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epm3064a

Manufacturer Part Number
epm3064a
Description
Programmable Logic Device Family
Manufacturer
Altera Corporation
Datasheet

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MAX 3000A Programmable Logic Device Family Data Sheet
16
Table 4. MAX 3000A t
Table 5. MAX 3000A In-System Programming Times for Different Test Clock Frequencies
Table 6. MAX 3000A Stand-Alone Verification Times for Different Test Clock Frequencies
EPM3032A
EPM3064A
EPM3128A
EPM3256A
EPM3512A
EPM3032A
EPM3064A
EPM3128A
EPM3256A
EPM3512A
Device
Device
EPM3032A
EPM3064A
EPM3128A
EPM3256A
EPM3512A
Device
10 MHz
10 MHz
2.01
2.01
2.02
2.05
2.09
0.00
0.01
0.01
0.02
0.03
PULSE
5 MHz
5 MHz
The programming times described in
with the worst-case method using the enhanced ISP algorithm.
Tables 5
verification times for several common test clock frequencies.
& Cycle
2.01
2.02
2.04
2.09
2.18
0.01
0.01
0.02
0.03
0.06
t
PPULSE
2.00
2.00
2.00
2.00
2.00
TCK
and
2 MHz
2 MHz
2.03
2.05
2.10
2.23
2.45
0.01
0.02
0.04
0.08
0.15
(s)
Values
Programming
6
show the in-system programming and stand alone
1 MHz
1 MHz
2.06
2.11
2.21
2.45
2.89
0.02
0.04
0.07
0.15
0.30
Cycle
105,000
205,000
447,000
890,000
55,000
f
f
TCK
TCK
PTCK
500 kHz
500 kHz
2.11
2.21
2.41
2.90
3.78
0.04
0.07
0.14
0.30
0.60
200 kHz
Tables 4
200 kHz
2.28
2.53
3.03
4.24
6.45
0.09
0.18
0.34
0.75
1.49
t
VPULSE
0.002
0.002
0.002
0.002
0.002
Stand-Alone Verification
through
(s)
100 kHz
100 kHz
10.90
0.18
0.35
0.68
1.49
2.97
2.55
3.05
4.05
6.47
6
Altera Corporation
are associated
50 kHz
50 kHz
10.94
19.80
0.36
0.70
1.36
2.98
5.94
Cycle
3.10
4.10
6.10
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