epm3064a Altera Corporation, epm3064a Datasheet - Page 35

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epm3064a

Manufacturer Part Number
epm3064a
Description
Programmable Logic Device Family
Manufacturer
Altera Corporation
Datasheet

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Altera Corporation
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IN
IO
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
CNT
CNT
ACNT
ACNT
Table 22. EPM3256A External Timing Parameters
Table 23. EPM3256A Internal Timing Parameters (Part 1 of 2)
Symbol
Symbol
Input pad and buffer delay
I/O input pad and buffer delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay,
slow slew rate = off
V
Output buffer and pad delay,
slow slew rate = off
V
Output buffer and pad delay,
slow slew rate = on
V
Output buffer enable delay, slow
slew rate = off V
Output buffer enable delay, slow
slew rate = off V
Minimum global clock
period
Maximum internal global
clock frequency
Minimum array clock
period
Maximum internal array
clock frequency
CCIO
CCIO
CCIO
= 3.3 V
= 2.5 V
= 2.5 V or 3.3 V
Parameter
Parameter
CCIO
CCIO
= 3.3 V
= 2.5 V
(2)
(2),
(2)
(2),
Conditions
(4)
(4)
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
MAX 3000A Programmable Logic Device Family Data Sheet
Conditions
Note (1)
126.6
126.6
Min
Min
–7
Note (1)
Max
–7
Speed Grade
7.9
7.9
Max
Speed Grade
0.9
0.9
2.8
0.5
2.2
1.0
0.0
1.2
1.7
6.2
4.0
4.5
95.2
95.2
Min
Min
–10
–10
Max
10.5
10.5
Max
1.2
1.2
3.7
0.6
2.8
1.3
0.0
1.6
2.1
6.6
5.0
5.5
Unit
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35

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