xc2c64a-7pcg44i Xilinx Corp., xc2c64a-7pcg44i Datasheet - Page 2

• Manufacturer Part Number: xc2c64a-7pcg44i
• Description: Xc2c64a Coolrunner-ii Cpld
• Manufacturer: Xilinx Corp.

XC2C64A CoolRunner-II CPLD
RealDigital Design Technology
Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron
process technology which is derived from leading edge
FPGA product development. CoolRunner-II CPLDs employ
RealDigital, a design technique that makes use of CMOS
technology in both the fabrication and design methodology.
RealDigital design technology employs a cascade of CMOS
gates to implement sum of products instead of traditional
sense amplifier methodology. Due to this technology, Xilinx
CoolRunner-II CPLDs achieve both high performance and
low power operation.
Supported I/O Standards
The CoolRunner-II 64 macrocell features both LVCMOS
and LVTTL I/O implementations. See
dard voltages. The LVTTL I/O standard is a general purpose
EIA/JEDEC standard for 3.3V applications that use an
Table 2: I
2
Notes:
1.
Typical I
16-bit up/down, Resetable binary counter (one counter per function block).
CC
CC
(mA)
vs Frequency (LVCMOS 1.8V T
0.017
0
15
10
20
5
0
0
Table 1
1.8
25
A
for I/O stan-
Figure 1: I
50
= 25°C)
3.7
50
www.xilinx.com
(1)
100
5.5
75
CC
vs Frequency
Frequency (MHz)
LVTTL input buffer and Push-Pull output buffer. The
LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications.
CoolRunner-II CPLDs are also 1.5V I/O compatible with the
use of Schmitt-trigger inputs.
Table 1: I/O Standards for XC2C64A
(1) LVCMOS15 requires Schmitt-trigger inputs.
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
IOSTANDARD
7.48
100
Attribute
150
Frequency (MHz)
11.0
150
(1)
200
Output
DS092_01_092302
V
3.3
3.3
2.5
1.8
1.5
CCIO
12.7
175
250
V
Input
3.3
CCIO
3.3
2.5
1.8
1.5
14.6
200
DS311 (v2.2) March 8, 2007
Input
V
N/A
N/A
N/A
N/A
N/A
Product Specification
REF
15.3
225
Termination
Voltage V
Board
N/A
N/A
N/A
N/A
N/A
17.77
240
T
R