xc2c64-7vq44c Xilinx Corp., xc2c64-7vq44c Datasheet

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xc2c64-7vq44c

Manufacturer Part Number
xc2c64-7vq44c
Description
Xc2c64 Coolrunner-ii Cpld
Manufacturer
Xilinx Corp.
Datasheet

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Part Number:
XC2C64-7VQ44C
Manufacturer:
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DS092 (v1.0) December 19, 2001
Features
Refer to the CoolRunner™-II family data sheet for architec-
ture description.
DS092 (v1.0) December 19, 2001
Advance Product Specification
Industries best 0.18 micron CMOS CPLD
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Available in multiple package styles
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Optimized for high performance 1.8V systems
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Advanced system features
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© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
4.0 ns pin-to-pin logic delays
less than 100 A standby current consumption
64 macrocells with up to 1,600 logic gates
Fast input registers
Slew rate control on individual outputs
LVCMOS 1.8V through 3.3V
LVTTL 3.3V
44-pin PLCC with 33 user I/O
44-pin VQFP with 33 user I/O
56-ball CP (0.05mm) BGA with 45 user I/O
100-pin VQFP with 64 user I/O
Ultra low power operation
Advanced 0.18 micron 4-metal layer Non-volatile
process
Quadruple enhanced security
Multi-voltage system interface
Hot pluggable
IEEE1532 In-system programmable
Superior pin locking through PLA array
Input hysteresis (Schmitt trigger) on all pins
Bus hold circuitry on all user pins
IEEE standard 1149.1 boundary scan (JTAG)
Fast programming times
Excellent pin retention during design changes
High quality and reliability
Guaranteed 10,000 program/erase cycles
20 year data retention
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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www.xilinx.com
1-800-255-7778
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XC2C64 CoolRunner-II CPLD
Advance Product Specification
Description
The CoolRunner-II 64-macrocell device is designed for both
high performance and low power applications. This lends
power savings to high-end communication equipment and
speed to battery operated devices.
This device consists of four Function Blocks inter-con-
nected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 inputs to each Function Block. The Func-
tion Blocks consist of a 40 by 56 p-term PLA and 16 macro-
cells which contain numerous configuration bits that allow
for combinational or registered modes of operation. Addi-
tionally, these registers can be globally reset or preset and
configured as a D or T flip-flop or as a D latch. There are
also multiple clock signals, both global and local product
term based, on a per macrocell basis. Output control sig-
nals include slew rate control, bus hold and open drain. An
additional Schmitt-trigger input is available on a per input
pin basis.
In addition to combinatorial and registered outputs, the reg-
isters may be configured as fast inputs.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. Global clocks are additionally
used to set or preset individual macrocell registers on
power up. Local clocks are generated in specific Function
Blocks and only available to macrocell registers in that
Function Block.
A DualEDGE flip-flop feature is also available on a per mac-
rocell basis. This feature allows performance where it is
needed without raising the total power consumption of the
entire device.
The CoolRunner-II 64-macrocell CPLD is I/O compatible
with standard LVTTL33 and LVCMOS18, 25, and 33 volts
(see Table 1).
Fast Zero Power Design Technology
All CoolRunner-II CPLDs employ Fast Zero Power™ (FZP),
a design technique that employs CMOS technology in both
the fabrication and design methodology. Xilinx CoolRun-
ner-II is fabricated on a 0.18 micron process technology
which is derived from leading edge FPGA product develop-
ment. CoolRunner-II design technology employs a cascade
of CMOS gates to implement sum of products instead of tra-
ditional sense amplifier methodology. Due to this FZP tech-
nology, Xilinx CoolRunner-II CPLDs achieve both high
performance and low power operation.
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xc2c64-7vq44c Summary of contents

Page 1

... Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS092 (v1.0) December 19, 2001 Advance Product Specification 0 XC2C64 CoolRunner-II CPLD Advance Product Specification 0 0 Description The CoolRunner-II 64-macrocell device is designed for both high performance and low power applications ...

Page 2

... It does not require the use of a reference voltage or termination voltage Table Frequency (LVCMOS 1. Typical I (mA) 3.6 5 Table 1: I/O Standards for XC2C64 Table 1 for I/O stan- I/O Standard LVTTL LVCMOS33 LVCMOS25 LVCMOS18 50 100 150 200 Frequency (MHz) Figure Frequency CC = 25° Frequency (MHz) ...

Page 3

... V IN CCIO CCIO V = 1.9V 3.6V CC CCIO MHz MHz MHz MHz MHz www.xilinx.com 1-800-255-7778 XC2C64 CoolRunner-II CPLD Value Units –0.5 to 2.0 V –0.5 to 4.0 V –0.5 to 4.0 V –0.5 to 4.0 V –65 to +150 ° ° °C Min Max Units 1 ...

Page 4

... XC2C64 CoolRunner-II CPLD LVCMOS 3.3V DC Voltage Specifications Symbol Parameter V Input source voltage CCIO V High level input voltage IH V Low level input voltage IL V High level output voltage OH V Low level input voltage OL I Input leakage current IL I I/O High-Z leakage IH C JTAG input capacitance ...

Page 5

... V OH CCIO CCIO mA CCIO I = 0.1 mA CCIO 3.9V IN CCIO 3.9V IN CCIO MHz MHz MHz www.xilinx.com 1-800-255-7778 XC2C64 CoolRunner-II CPLD Min. Max. Units 1.7 1.9 V 3.9 V CCIO –0.3 0 CCIO -0. -0 0.45 0.2 V – –10 ...

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... XC2C64 CoolRunner-II CPLD AC Electrical Characteristics Over Recommended Operating Conditions Symbol Parameter T Propagation delay single p-term PD1 T Propagation delay OR array PD2 T Setup time fast SU1 T Setup time SU2 T Fast input register hold time H1 T P-term hold time H2 T Clock to output CO T Internal toggle rate ...

Page 7

... IN18 T Hysteresis input adder HYS18 T Output adder OUT18 T Output slew rate adder SLEW I/O Standard Time Adder Delays 2.5V CMOS DS092 (v1.0) December 19, 2001 Advance Product Specification -4 (1) Min. Max. - 1.3 - 1.6 - 1.2 - 1.9 - 1.4 - 1.6 - 2.5 - 0.5 - 0.4 - 0.3 - 0 0 1 2.0 www.xilinx.com 1-800-255-7778 XC2C64 CoolRunner-II CPLD -5 -7 Min. Max. Min. Max. - 1.7 - 2.4 - 2.1 - 3.0 - 1.6 - 2.5 - 2.4 - 3.5 - 1.9 - 3.0 - 1.9 - 2.8 - 3.0 - 4.0 - 0.6 - 0.9 - 0.5 - 0.8 - 0.4 - 0.8 - 0.5 - 0.7 1 1 ...

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... XC2C64 CoolRunner-II CPLD Internal Timing Parameters (Continued) Symbol Parameter T Standard input adder IN25 T Hysteresis input adder HYS25 T Output adder OUT25 T Output slew rate adder SLEW25 I/O Standard Time Adder Delays 3.3V CMOS/TTL T Standard input adder IN33 T Hysteresis input adder HYS33 T Output adder OUT33 ...

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... Note: GTS = global output enable, GRS = global reset/set, GCK = global clock x www.xilinx.com 1-800-255-7778 XC2C64 CoolRunner-II CPLD Macro- cell PC44 VQ44 CP56 ...

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... CCIO Ground No connects Total user I/O Ordering Information Pin/Ball Part Number Spacing XC2C64-4PC44C 1.27mm XC2C64-5PC44C 1.27mm XC2C64-7PC44C 1.27mm XC2C64-4VQ44C 0.8mm XC2C64-5VQ44C 0.8mm XC2C64-7VQ44C 0.8mm XC2C64-4CP56C 0.5mm XC2C64-5CP56C 0.5mm XC2C64-7CP56C 0.5mm XC2C64-4VQ100C 0.5mm XC2C64-5VQ100C 0.5mm XC2C64-7VQ100C 0.8mm XC2C64-5PC44I 1.27mm XC2C64-7PC44I 1.27mm XC2C64-5VQ44I 0.8mm XC2C64-7VQ44I 0 ...

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... I/O CP56 I/O I/O Bottom View I/O I/O (1) V AUX (1) I/O I/O I/O V GND CCIO (3) (1) I/O I/O I/O I/O I/O TDO Figure 4: CP56 Package www.xilinx.com 1-800-255-7778 XC2C64 CoolRunner-II CPLD VQ44 Top View (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset Figure 3: VQ44 Package ...

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... XC2C64 CoolRunner-II CPLD 1 (1) I/O 2 (1) I/O 3 (1) I/O 4 (1) I AUX 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I GND (2) 22 I/O (2) 23 I/O I (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset Revision History The following table shows the revision history for this document. ...

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