xc2c32a-6vq44i Xilinx Corp., xc2c32a-6vq44i Datasheet

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xc2c32a-6vq44i

Manufacturer Part Number
xc2c32a-6vq44i
Description
Xc2c32a Coolrunner-ii Cpld
Manufacturer
Xilinx Corp.
Datasheet

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DS310 (v2.0) March 8, 2007
Features
Refer to the CoolRunner™-II family data sheet for architec-
ture description.
DS310 (v2.0) March 8, 2007
Product Specification
© 2004-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
Optimized for 1.8V systems
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Industry’s best 0.18 micron CMOS CPLD
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Available in multiple package options
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Advanced system features
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As fast as 3.8 ns pin-to-pin logic delays
As low as 12 μA quiescent current
Optimized architecture for effective logic synthesis
Multi-voltage I/O operation: 1.5V through 3.3V
32-land QFN with 21 user I/O
44-pin PLCC with 33 user I/O
44-pin VQFP with 33 user I/O
56-ball CP BGA with 33 user I/O
Pb-free available for all packages
Fastest in system programming
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IEEE1149.1 JTAG Boundary Scan Test
Optional Schmitt-trigger input (per pin)
Two separate I/O banks
RealDigital 100% CMOS product term generation
Flexible clocking modes
Optional DualEDGE triggered registers
Global signal options with macrocell control
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Efficient control term clocks, output enables and
set/resets for each macrocell and shared across
function blocks
Advanced design security
Open-drain output option for Wired-OR and LED
drive
Optional configurable grounds on unused I/Os
Optional bus-hold, 3-state or weak pullup on
selected I/O pins
Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
PLA architecture
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Hot pluggable
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
1.8V ISP using IEEE 1532 (JTAG) interface
Multiple global clocks with phase selection per
macrocell
Multiple global output enables
Global set/reset
Superior pinout retention
100% product term routability across function
block
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XC2C32A CoolRunner-II CPLD
Product Specification
Description
The CoolRunner
both high performance and low power applications. This
lends power savings to high-end communication equipment
and high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reli-
ability is improved
This device consists of two Function Blocks interconnected
by a low power Advanced Interconnect Matrix (AIM). The
AIM feeds 40 true and complement inputs to each Function
Block. The Function Blocks consist of a 40 by 56 P-term
PLA and 16 macrocells which contain numerous configura-
tion bits that allow for combinational or registered modes of
operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds. A Schmitt trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers may be
configured as "direct input" registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. Macrocell registers can be
individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchro-
nous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
The CoolRunner-II 32-macrocell CPLD is I/O compatible
with standard LVTTL and LVCMOS18, LVCMOS25, and
LVCMOS33 (see
patible with the use of Schmitt-trigger inputs.
Another feature that eases voltage translation is I/O bank-
ing. Two I/O banks are available on the CoolRunner-II 32A
macrocell device that permit easy interfacing to 3.3V, 2.5V,
1.8V, and 1.5V devices.
Table
-II 32-macrocell device is designed for
1). This device is also 1.5V I/O com-
1

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xc2c32a-6vq44i Summary of contents

Page 1

... Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS310 (v2.0) March 8, 2007 Product Specification 0 XC2C32A CoolRunner-II CPLD Product Specification 0 0 Description ™ ...

Page 2

... CC Notes: 1. 16-bit up/down, resettable binary counter (one counter per function block). 2 LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications. CoolRunner-II CPLDs are also 1.5V I/O compatible with the use of Schmitt-trigger inputs. Table 1: I/O Standards for XC2C32A IOSTANDARD Attribute LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 (1) LVCMOS15 requires Schmitt-trigger inputs. ...

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... MHz MHz MHz MHz MHz 3.9V IN CCIO 3.9V IN CCIO www.xilinx.com XC2C32A CoolRunner-II CPLD Value Units –0.5 to 2.0 V –0.5 to 4.0 V –0.5 to 4.0 V –0.5 to 4.0 V –0.5 to 4.0 V –0.5 to 4.0 V –65 to +150 °C +150 °C ...

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... XC2C32A CoolRunner-II CPLD LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications Symbol Parameter V Input source voltage CCIO V High level input voltage IH V Low level input voltage IL V High level output voltage OH V Low level output voltage OL LVCMOS 2.5V DC Voltage Specifications Symbol Parameter V Input source voltage ...

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... Global clock pulse width High or Low CW T P-term pulse width High or Low PCW DS310 (v2.0) March 8, 2007 Product Specification Test Conditions mA 1.4V OL CCIO I = 0.1 mA 1.4V OL CCIO Test Conditions Parameter www.xilinx.com XC2C32A CoolRunner-II CPLD Min. Max. Units - 0 0.2 V Min. Max. Units 1.4 3 CCIO CCIO ...

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... XC2C32A CoolRunner-II CPLD Symbol T Asynchronous preset/reset pulse width (High or Low) APRPW (4) T Configuration time CONFIG Notes the maximum clock frequency to which a T-Flip Flop can reliably toggle (see the CoolRunner-II family data sheet). TOGGLE the internal operating frequency for a device fully populated with one 16-bit counter through one p-term per ...

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... Output adder OUT15 T Output slew rate adder SLEW15 I/O Standard Time Adder Delays 1.8V CMOS T Hysteresis input adder HYS18 T Output adder OUT18 T Output slew rate adder SLEW DS310 (v2.0) March 8, 2007 Product Specification -4 (1) Min. Max 1.5 0.0 0.7 0 www.xilinx.com XC2C32A CoolRunner-II CPLD -6 Min. Max. Units 1.3 - 1.7 1.5 - 2.4 1.3 - 2.0 1.6 - 2.0 1.1 - 2.1 1.8 - 2.0 2.9 - 3.4 1.3 - 1.6 0.4 - 1.1 0.2 - 0.5 0.3 - 0.7 1.5 - 2 ...

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... XC2C32A CoolRunner-II CPLD Internal Timing Parameters (Continued) Symbol Parameter I/O Standard Time Adder Delays 2.5V CMOS T Standard input adder IN25 T Hysteresis input adder HYS25 T Output adder OUT25 T Output slew rate adder SLEW25 I/O Standard Time Adder Delays 3.3V CMOS/TTL T Standard input adder IN33 T Hysteresis input adder ...

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... DS310 (v2.0) March 8, 2007 Product Specification 3.3V 2.5V 1.5V .5 1.0 1.5 2.0 VO (Output Volts) Figure 4: Typical I/V Curve for XC2C32A QFG32 PC44 ...

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... Notes: 1. GTS = global output enable, GSR = global set reset, GCK = global clock 2. GTS, GSR, and GCK pins can also be used for general purpose I/O. XC2C32A Global, JTAG, Power/Ground and No Connect Pins Pin Type TCK TDI TDO TMS Input Only V (JTAG supply voltage) ...

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... XC2C32A-6CP56C 0.5mm XC2C32A-4PCG44C 1.27mm XC2C32A-6PCG44C 1.27mm XC2C32A-4VQG44C 0.8mm XC2C32A-6VQG44C 0.8mm XC2C32A-4CPG56C 0.5mm XC2C32A-6CPG56C 0.5mm XC2C32A-6QFG32I 0.5mm XC2C32A-6PC44I 1.27mm XC2C32A-6VQ44I 0.8mm XC2C32A-6CP56I 0.5mm XC2C32A-6PCG44I 1.27mm DS310 (v2.0) March 8, 2007 Product Specification θ θ (C/Watt) (C/Watt) Package Type 35.5 24.0 Quad Flat No Lead; Pb-free 35 ...

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... XC2C32A CoolRunner-II CPLD Pin/Ball Part Number Spacing XC2C32A-6VQG44I 0.8mm XC2C32A-6CPG56I 0.5mm Notes Commercial (T = 0°C to +70°C Industrial (T A Standard Example: XC2C128 -4 TQ Device Speed Grade Package Type Number of Pins Temperature Range Device Part Marking Device Type Package Speed Operating Range Note: Due to the small size of chip scale and quad flat no lead packages, the complete ordering part number cannot be included on the package marking ...

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... I/O Gnd 21 I Vcc CCIO1 I/O 19 I/O TDI TMS 18 I/O TCK 17 I/O (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset I/O (2) I/O I/O GND I/O I/O V CCIO1 I/O TDI TMS TCK www.xilinx.com XC2C32A CoolRunner-II CPLD VQ44 I I/O 6 Top View 28 I CCIO2 GND 9 25 TDO ...

Page 14

... XC2C32A CoolRunner-II CPLD K I/O J I/O H I/O G I/O F I/O E I/O D I/O C I/O B I/O A I/O (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset Warranty Disclaimer THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS ...

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... Device Packages Revision , t , and t TOGGLE SLEW25 SLEW33 , T IN25 specification for 2.5V and 1.8V LVCMOS. Change for LVCMOS18; removed note for V IL www.xilinx.com XC2C32A CoolRunner-II CPLD . CCSB , T , and T . OUT25 IN33 OUT33 GCK, GSR, and GTS pins can also for -4 speed OEM for LVCMOS33. IL ...

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... XC2C32A CoolRunner-II CPLD 16 www.xilinx.com R DS310 (v2.0) March 8, 2007 Product Specification ...

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