atv2500h-35pi ATMEL Corporation, atv2500h-35pi Datasheet

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atv2500h-35pi

Manufacturer Part Number
atv2500h-35pi
Description
High-density Uv-erasable Programmable Logic Device - Atmel Corporation
Manufacturer
ATMEL Corporation
Datasheet
Features
Block Diagram
Description
The ATV2500H/L is the most powerful programmable logic device available in a 40-
pin package. Increased product terms, sum terms, and flip-flops translate into many
more usable gates. High gate utilization is easily obtainable.
The ATV2500H/L is organized around a global bus. All pin and feedback terms are
always available to every logic cell. Each of the 38 logic pins and their complements
are array inputs, as well as the true and false outputs of each of the 48 flip-flops.
Pin Configurations
Pin Name
IN
I/O
I/O, 0,2,4..
I/O, 1,3,5..
*
VCC
Third Generation Programmable Logic Structure
Increased Logic Flexibility
Flexible Output Macrocell
High-Speed
Low-Power — Less than 0.5 mA Typical (ATV2500L)
Multiple Feedback Paths Provide for Buried State Machines
and I/O Bus Compatibility
Asynchronous Clocks and Resets
Proven and Reliable High Speed CMOS EPROM Process
Reprogrammable - Tested 100% for Programmability
40-pin Dual-In-line and 44-Lead Surface Mount Packages
– Easily Achieves Gate Utilization Factors of 80 Percent
– 86 Inputs and 72 Sum Terms
– 48 Flip-Flops - 2 per Macrocell
– 3 Sum Terms - Can Be OR'ed and Shared
– Multiple Synchronous Presets - One per Four or Eight Flip-Flops
– 2000V ESD Protection
– 200 mA Latchup Immunity
Function
Logic Inputs
Bidirectional Buffers
“Even” I/O Buffers
“Odd” I/O Buffers
No Internal Connection
+5V Supply
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
VCC
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
IN
IN
IN
IN
IN
IN
IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DIP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
IN
IN
IN
IN
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
GND
I/O23
I/O22
I/O21
I/O20
I/O19
I/O18
IN
IN
IN
* = No Connect
I/O17
I/O16
I/O15
I/O14
I/O13
VCC
VCC
I/O2
I/O3
I/O4
I/O5
7
8
9
10
11
12
13
14
15
16
17
PLCC/LCC
(continued)
39
38
37
36
35
34
33
32
31
30
29
I/O7
I/O8
I/O9
I/O10
I/O11
GND
GND
I/O23
I/O22
I/O21
I/O20
High-Density
UV-Erasable
Programmable
Logic Device
ATV2500H
ATV2500L
Rev. 0025E–05/98
1

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atv2500h-35pi Summary of contents

Page 1

... Increased product terms, sum terms, and flip-flops translate into many more usable gates. High gate utilization is easily obtainable. The ATV2500H/L is organized around a global bus. All pin and feedback terms are always available to every logic cell. Each of the 38 logic pins and their complements are array inputs, as well as the true and false outputs of each of the 48 flip-flops ...

Page 2

... Independent of output config- uration, the two flip-flops are always usable, and always have at least four product term inputs. Functional Logic Diagram ATV2500H/L ATV2500H/L 2 Product terms are available providing asynchronous resets, flip-flop clocks, and output enables. One reset and one clock term are provided per flip-flop, with one enable term per output ...

Page 3

... All interconnections are routed through the glo- bal bus. The ATV2500H straightforward and uniform PLD. The twenty-four macrocells are numbered 0 through 23. Each macrocell contains 17 AND gates. All AND gates have 172 inputs. The five lower product terms provide AR1, CK1, CK2, AR2, and OE ...

Page 4

... Combinatorial (8 Terms Combinatorial (4 Terms) (1) ( Combinatorial (12 Terms) 1. These 4 terms are shared with D1. Output Configuration Active Low Active High ATV2500H/L-30 ATV2500H/ 125 C - 125 C 5V 10% 5V 10% ...

Page 5

... Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. = -0. -0. 0.1V OUT CC = MAX, ATV2500L Com GND Ind.,Mil. ATV2500H Com. Ind.,Mil. = 0.5V OUT = IL Com,Ind Mil. = -100 A = -4.0 mA (1) Max Units 6 ...

Page 6

... Maximum Frequency (1/t MAX t Asynchronous Reset Width AW t Asynchronous Reset Recovery Time AR t Asynchronous Reset to AP Registered Output Reset Note: 1. Buried registers include all 24 Q2 registers and any of the 24 Q1 registers in macrocells configured as combinatorial. ATV2500H/L 6 ATV2500L-30 Min Max ( ...

Page 7

... AC Characteristics for the ATV2500H Symbol Parameter t Input or Feedback to PD Non-Registered Output t Input to Output Enable EA t Input to Output Disable ER t Clock to Output CO t Clock to Feedback CF t Input Setup SI1 Time, Output Register t Input Setup SI2 Time, Buried Register t Feedback Setup Time SF t Hold Time ...

Page 8

... V High IL Power-Up Reset The registers in the ATV2500H/L are designed to reset dur- ing power-up point delayed slightly from V 3.8V, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. This feature is critical for state machine initialization. How- ...

Page 9

... PLD software vendors. Please refer to the Pro- grammable Logic Development Tools section for a com- plete listing of the PLD software support. Erasure Characteristics The entire memory array of an ATV2500H/L is erased after exposure to ultraviolet light at a wavelength of 2537 Å. Complete erasure is assured after a minimum of twenty minutes exposure using 12,000 W/cm spaced one inch away from the chip ...

Page 10

... Note: All normalized values referenced to maximum specification in AC characteristics section of datasheet. ATV2500H/L 10 ...

Page 11

11 ...

Page 12

... ATV2500H-30KC ATV2500H-30LC ATV2500H-30PC ATV2500H-30DI ATV2500H-30JI ATV2500H-30KI ATV2500H-30LI ATV2500H-30PI ATV2500H-35DC ATV2500H-35JC ATV2500H-35KC ATV2500H-35LC ATV2500H-35PC ATV2500H-35DI ATV2500H-35JI ATV2500H-35KI ATV2500H-35LI ATV2500H-35PI 5962-91545 02M QA 5962-91545 02M XX 5962-91545 02M YX Package Operation Range 40DW6 Commercial 44J ( 44KW 44LW 40P6 40DW6 Industrial 44J (- 44KW ...

Page 13

Ordering Information (Continued MAX (ns) (ns) (MHz 40DW6 40-Lead, 0.600" Wide Windowed, Ceramic Dual In-line Package (Cerdip) 44J 44-Lead, Plastic J-Leaded Chip Carrier OTP (PLCC) 44KW ...

Page 14

... TYP .500(12.7) REF SQ .025(.635) RADIUS MAX (3X) ATV2500H/L 14 44J, 44-Lead, Plastic J-Leaded Chip Carrier OTP (PLCC) Dimensions in Inches and (Millimeters) .032(.813) .026(.660) .050(1.27) TYP 44LW, 44-Pad, Windowed, Ceramic Leadless Chip ...

Page 15

Packaging Information 40P6, 40-Lead, 0.600" Wide Plastic Dual Inline Package OTP (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-001 AC 2.07(52.6) 2.04(51.8) 1.900(48.26) REF .220(5.59) MAX SEATING PLANE .161(4.09) .125(3.18) .065(1.65) .110(2.79) .041(1.04) .090(2.29) .630(16.0) .590(15.0) .012(.305) .008(.203) .690(17.5) ...

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