adsp-21061l Analog Devices, Inc., adsp-21061l Datasheet
adsp-21061l
Available stocks
Related parts for adsp-21061l
adsp-21061l Summary of contents
Page 1
... REGISTERS ALU STATUS AND DATA BUFFERS Figure 1. Functional Block Diagram One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel : 781.329.4700 Fax: 781.461.3113 Commercial Grade Family DSP Microcomputer ADSP-21061/ADSP-21061L For more information, see Ordering JTAG TEST AND EMULATION I/O PORT ADDR DATA DATA ADDR ...
Page 2
... ADSP-21061/ADSP-21061L Parallel Computations Single-cycle multiply and ALU operations in parallel with dual memory read/write and instruction fetch Multiply with add and subtract for accelerated FFT butterfly computation 1M bit On-Chip SRAM Dual-ported for independent access by core processor and DMA Off-Chip Memory Interfacing 4 gigawords addressable ...
Page 3
... Ordering Guide ......................................................53 GENERAL NOTE This data sheet represents production released specifications for the ADSP-21061 (5 V) and ADSP-21061L (3.3 V) processors for 33 MHz, 40 MHz, 44 MHz, and 50 MHz speed grades. The product name“ADSP-21061” is used throughout this data sheet to represent all devices, except where expressly noted. ...
Page 4
... DMAR RCLK1 1–2 TFS1 DMAG 1–2 RSF1 CS DT1 DR1 HBR HBG REDY BR RPBA 1–6 ID CPA 2–0 RESET JTAG 7 Figure 2. ADSP-21061/ADSP-21061L System Sample Configuration CS BOOT EPROM ADDR (OPTIONAL) DATA ADDR MEMORY- DATA MAPPED OE DEVICES WE (OPTIONAL) ACK CS DMA DEVICE (OPTIONAL) DATA HOST PROCESSOR ...
Page 5
... The ADSP-21061’s on-chip DMA controller allows zero- overhead data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. Rev Page July 2007 ADSP-21061/ADSP-21061L ...
Page 6
... ADSP-21061/ADSP-21061L 3 011 3 010 3 001 BUS PRIORITY RESET CLOCK DMA transfers can occur between the ADSP-21061’s internal memory and either external memory, external peripherals host processor. DMA transfers can also occur between the ADSP-21061’s internal memory and its serial ports. ...
Page 7
... WITH ID = 100 0x0028 0000 WITH ID = 101 0x0030 0000 WITH ID = 110 0x0038 0000 BROADCAST WRITE TO ALL ADSP-21061s 0x003F FFFF Figure 4. Memory Map Rev Page July 2007 ADSP-21061/ADSP-21061L Figure ADDRESS 0x0040 0000 BANK 0 MS0 SDRAM (OPTIONAL) MS1 BANK 1 MS2 BANK 2 ...
Page 8
... ADSP-21061/ADSP-21061L Program Booting The internal memory of the ADSP-21061 can be booted at sys- tem power-up from either an 8-bit EPROM host processor. Selection of the boot source is controlled by the BMS (boot memory select), EBOOT (EPROM boot), and LBOOT (host boot) pins. 32-bit and 16-bit host processors can be used for booting ...
Page 9
... ADDITIONAL INFORMATION ®† evaluation plat- This data sheet provides a general overview of the ADSP-21061 architecture and functionality. For detailed information on the ADSP-21000 Family core architecture and instruction set, refer to the ADSP-21061 SHARC User’s Manual, Revision 2.1. Rev Page July 2007 ADSP-21061/ADSP-21061L ...
Page 10
... ADSP-21061/ADSP-21061L PIN FUNCTION DESCRIPTIONS ADSP-21061 pin definitions are listed below. All pins are identi- cal on the ADSP-21061 and ADSP-21061L. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identi- fied as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST) ...
Page 11
... Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kΩ internal pull-up resistor Asynchronous Ground Input Output Power Supply Synchronous, (A/D) = Active Drive, (O/D) = Open-Drain Three-State (when SBTS is asserted, or when the ADSP-21061 is a bus slave) Rev Page July 2007 ADSP-21061/ADSP-21061L in a 6–1 ...
Page 12
... ADSP-21061/ADSP-21061L Table 2. Pin Descriptions (Continued) Pin Type Function TFSx I/O Transmit Frame Sync (Serial Ports 0, 1). RFSx I/O Receive Frame Sync (Serial Ports 0, 1). EBOOT I EPROM Boot Select. When EBOOT is high, the ADSP-21061 is configured for booting from an 8-bit EPROM. When EBOOT is low, the LBOOT and BMS inputs determine booting mode. See the table in the BMS pin description below ...
Page 13
... CLKIN is not connected), just use appropriate parallel termina- tion on TCK and TMS. TDI, TDO, EMU, and TRST are not critical signals in terms of skew. For complete information on the SHARC EZ-ICE, see the ADSP-21000 Family JTAG EZ-ICE User's Guide and Reference. Rev Page July 2007 ADSP-21061/ADSP-21061L ...
Page 14
... ADSP-21061/ADSP-21061L OTHER JTAG CONTROLLER Figure 6. JTAG Scan Path Connections for Multiple ADSP-2106x Systems TDI EMU TCK TMS TRST TDO CLKIN ADSP-2106x #1 TDI TDO TDI TDI EZ-ICE JTAG CONNECTOR TCK TMS EMU TRST TDO CLKIN OPTIONAL TDI TDO TDI TDO 5k * TDI TDO ...
Page 15
... Max 1 25° 2 HBG, REDY, DMAG1, DMAG2, BMS, BR 3–0 = 001 and another ADSP-21061 is not requesting bus 2–0 = 001 and another ADSP-21061L 2–0 Unit V ° RPBA, CPA, TFS0, 2–0 Max Unit V 0 μA 10 μ ...
Page 16
... composite average based on a range of low activity code. DDINLOW 4 Idle denotes ADSP-21061L state during execution of IDLE instruction. 5 Idle16 denotes ADSP-2106x state during execution of IDLE16 instruction. a complete discussion of the code used to measure power dissi- pation, see the technical note “SHARC Power Dissipation DD Measurements.” ...
Page 17
... EXT cannot INT Rev Page July 2007 ADSP-21061/ADSP-21061L ), but selects can switch on each cycle. CK with the following assumptions: EXT (32-bit 1/(4t ), with 50% of the pins switching CK CK equation is calculated for each class of pins that can EXT × ...
Page 18
... V Max 1 25° 2 HBG, REDY, DMAG1, DMAG2, BMS, BR 3–0 = 001 and another ADSP-21061 is not requesting bus 2–0 = 001 and another ADSP-21061L 2–0 Unit V ° RPBA, CPA, TFS0, 2–0 Max Unit V 0 μ ...
Page 19
... IDDINLOW 4 Idle denotes ADSP-21061L state during execution of IDLE instruction. 5 Idle16 denotes ADSP-21061L state during execution of IDLE16 instruction. a complete discussion of the code used to measure power dissi- pation, see the technical note “SHARC Power Dissipation DD Measurements.” ...
Page 20
... ADSP-21061/ADSP-21061L EXTERNAL POWER DISSIPATION (3.3 V) Total power dissipation has two components, one due to inter- nal circuitry and one due to the switching of external output drivers. Internal power dissipation is dependent on the instruc- tion execution sequence and the data operands involved. Internal power dissipation is calculated in the following way: × ...
Page 21
... Switching characteristics tell you what the processor will given circumstance. You can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Rev Page July 2007 ADSP-21061/ADSP-21061L 3.3 V –0 +4.6 V +0.5 V –0 +0.5 V ...
Page 22
... CKH CKL Figure 9. Clock Input Min DT/2 t WRST Figure 10. Reset Rev Page July 2007 ADSP-21061/ ADSP-21061L 40 MHz, ADSP-21061 5 V and 3 MHz Max Min Max Min 100 25 100 and 3.3 V Max ...
Page 23
... Table 10. Timer Parameter Switching Characteristic t CLKIN High to TIMEXP DTEX CLKIN t DTEX TIMEXP SIR t HIR t IPW Figure 11. Interrupts Figure 12. Timer Rev Page July 2007 ADSP-21061/ADSP-21061L 5 V and 3.3 V Min Max 18 + 3DT 3DT/4 2 and 3.3 V Min Max 15 t DTEX Unit Unit ns ...
Page 24
... ADSP-21061/ADSP-21061L Flags Table 11. Flags Parameter Timing Requirements t FLAG3–0 IN Setup Before CLKIN High SFI t FLAG3–0 IN Hold After CLKIN High HFI t FLAG3–0 IN Delay After RD/WR Low DWRFI t FLAG3–0 IN Hold After RD/WR Deasserted HFIWR Switching Characteristics t FLAG3–0 OUT Delay After CLKIN High ...
Page 25
... Example System Hold Time Calculation on Page 44 HSDATI (Table 13 on Page SACKC DRLD t DAD t DSAK Figure 14. Memory Read—Bus Master Rev Page July 2007 ADSP-21061/ADSP-21061L 5 V and 3.3 V Min Max 5DT 0.5 2 7DT DT 0 3DT/8 12.5 + 5DT 3DT DT/4 ...
Page 26
... ADSP-21061/ADSP-21061L Memory Write—Bus Master Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-21061 is the Table 13. Memory Write—Bus Master Parameter Timing Requirements t ACK Delay from Address, Selects DAAK 1 t ACK Delay from WR Low ...
Page 27
... CK or synchronous specification t for deassertion of ACK (low), all three specifications must be met for assertion of ACK SAKC for calculation of hold times given capacitive and dc loads. Rev Page July 2007 ADSP-21061/ADSP-21061L 26). When accessing a slave ADSP-21061, Synchronous 29). The slave ADSP-21061 5 V and 3.3 V Min ...
Page 28
... ADSP-21061/ADSP-21061L CLKIN t DADCCK ADDRCLK t DADRO ADDRESS, BMS, SW, MSx PAGE ACK (IN) READ CYCLE RD DATA (IN) WRITE CYCLE WR DATA (OUT) t ADRCK t t ADRCKH ADRCKL t DAAK t DPGC t t DRWL t DRWL t SDDATO Figure 16. Synchronous Read/Write—Bus Master Rev Page July 2007 t HADRO t HACK SACKC t DRDO ...
Page 29
... WAIT register) is disabled; when MMSWS is enabled, t SRWLI 2 This specification applies to the ADSP-21061LKS-176 (3 MHz) and the ADSP-21061KS-200 ( MHz), operating at t preceding timing specification of the same name. 3 See Example System Hold Time Calculation on Page 44 ...
Page 30
... ADSP-21061/ADSP-21061L CLKIN ADDRESS, SW ACK READ ACCESS RD DATA (OU T) WRITE ACCESS W R DATA (IN WLI Figure 17. Synchronous Read/Write—Bus Slave Rev Page July 2007 ...
Page 31
... User’s Manual, Revision 2.1. 2 Only required for recognition in the current cycle. 3 CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN. 4 For the ADSP-21061L (3.3 V), this specification is 8.5 – DT/8 ns max. 5 (O/D) = open drain, (A/D) = active drive. 6 For the ADSP-21061L (3.3 V), this specification max. 7 For the ADSP-21061L (3 ...
Page 32
... ADSP-21061/ADSP-21061L CLKIN t SHBRI HBR HBG(OUT) BRx (OUT) CPA (OUT, O/D) HBG (IN) BRx, CPA (IN, O/D) RPBA HBR CS t DRDYCS REDY (O/D) REDY (A/D) HBG(OUT O/D = OPEN-DRAIN, A/D = ACTIVEDRIVE t HHBRI t DHBGO t HHBGO t DBRO t HBRO t DCPAO t SRPBAI t HRPBAI t TRDYHG t HBGRCSV Figure 18. Multiprocessor Bus Request and Host Bus Request Rev Page July 2007 ...
Page 33
... HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the HBGRCSV ADSP-21061” section in the ADSP-21061 SHARC User’s Manual, Revision 2.1. 2 For the ADSP-21061L (3.3 V), this specification is 13.5 ns max. Table 18. Write Cycle Parameter Timing Requirements ...
Page 34
... ADSP-21061/ADSP-21061L CLKIN REDY (O/D) REDY (A/D) READ CYCLE ADDRESS/CS RD DATA (O UT) REDY (O/D) REDY (A/D) WRITE CYCLE ADDRESS CS WR DATA (IN) REDY (O/D) REDY (A/ OPEN-DRAIN, A/D = ACT IVE DRIVE O/D = OPEN-DRAIN, A/D = ACTIVE DRIVE Figure 19. Synchronous REDY Timing DATR YPR ...
Page 35
... STSCK MIENA, MIENS, MIENHG t DATEN t ACKEN t ADCEN Rev Page July 2007 ADSP-21061/ADSP-21061L 5 V and 3.3 V Min Max DT/2 –1 – DT/8 –1.5 – DT/8 –1.5 – DT/8 0 – DT/4 1.5 – DT/4 2.0 – DT 5DT/16 0 – DT/8 7 – DT/8 7.5 + DT/4 –1 – DT/8 6 – DT/8 –2 – DT/8 8 – ...
Page 36
... ADSP-21061/ADSP-21061L HBG MEMORY INTERFACE MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW, PAGE, DMAGx. BMS (IN EPROM BOOT MODE) Figure 22. Three-State Timing (Bus Transition Cycle, SBTS Assertion) t MENHBG Rev Page July 2007 t MTRHBG ...
Page 37
... DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the data can SDATDGL be driven t after DMARx is brought high. DATDRH 3 For the ADSP-21061L (3.3 V), this specification is 23.5 + 7DT/8 ns min valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t VDATDGH the number of extra cycles that the access is prolonged. ...
Page 38
... ADSP-21061/ADSP-21061L CLKIN t SDRLC DMARx DMAGx TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE DATA (FROM ADSP-2106x TO EXTERNAL DEVICE) DATA (FROM EXTERNAL DEVICE TO ADSP-2106x) TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE) WR (EXTERNAL DEVICE TO EXTERNAL MEMORY) RD (EXTERNAL MEMORY TO EXTERNAL DEVICE) ...
Page 39
... Transmit Data Hold After TCLK HODTE 1 Referenced to drive edge RFS Setup Before RCLK Rev Page July 2007 ADSP-21061/ADSP-21061L 5 V and 3.3 V Min Max 3 and 3.3 V Min Max and 3.3 V Min Max ...
Page 40
... TCLK/RCLK Delay from CLKIN DCLK t SPORT Disable After CLKIN DPTR 1 Referenced to drive edge. 2 For the ADSP-21061L (3.3 V), this specification is 3.5 ns min. Table 27. Serial Ports—External Late Frame Sync Parameter Switching Characteristics t Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 0 DDTLFSE t ...
Page 41
... SPORT ENABLE AND THREE-STATE LATENCY TFS (EXT) IS TWO CYCLES NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O FOR MESH MULTIPROCESSING. Figure 24. Serial Ports Rev Page July 2007 ADSP-21061/ADSP-21061L SAMPLE EDGE t SCLKW t DFSE t t HFSE ...
Page 42
... ADSP-21061/ADSP-21061L RCLK RFS DT TCLK TFS DT EXTERNAL RFS WITH MCE = 1, MFD = 0 DRIVE SAMPLE DRIVE t t SFSE/I HOFSE/I t DDTE HDTE/I DDTENFS 1ST BIT t DDTLFSE LATE EXTERNAL TFS DRIVE SAMPLE DRIVE t HOFSE/I t SFSE/I t DDTE/I TDDTENFS t HDTE/I 1ST BIT t DDTLFSE Figure 25. Serial Ports—External Late Frame Sync Rev ...
Page 43
... SYSTEM INPUTS SYSTEM OUTPUTS Table 28 and TCK t t STAP HTAP t DTDO t DSYS Figure 26. JTAG Test Access Port and Emulation Rev Page July 2007 ADSP-21061/ADSP-21061L 5 V and 3.3 V Min Max 18 SSYS HSYS Unit ns ns ...
Page 44
... Figure 29. Voltage Reference Levels for AC Measurements (Except Output Output Drive Characteristics 27). If multiple Figure 30 output drivers of the ADSP-21061 (5 V) and ADSP-21061L (3 V). The curves represent the current drive capability and switching behavior of the output drivers as a function of resistive and capacitive loading. ...
Page 45
... Figure 32. Typical Output Rise Time (0 2.0 V) vs. Load Capacitance 3.75 4.50 5. NOMINAL 140 160 180 200 Figure 33. Typical Output Delay or Hold vs. Load Capacitance (at Maximum ) vs. Load Capacitance DD Rev Page July 2007 ADSP-21061/ADSP-21061L RISE TIME Y = 0.009x + 1.1 FALL TIME Y = 0.005x + 0 100 120 140 160 ...
Page 46
... ADSP-21061/ADSP-21061L Input/Output Characteristics (3.3 V) 120 100 3.3V, +25° 3.0V, +85° 3.0V, +85° 3.3V, +25° 100 OL - 120 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) Figure 34. Typical Drive Currents ( 0.0796x + 1. RISE TIME FALL TIME 100 120 LOAD CAPACITANCE (pF) Figure 35 ...
Page 47
... The slug is flush with the top surface of the package. Note that the metal slug is internally connected to GND through the device substrate. The ADSP-21061L is available in 240-lead MQFP and 225-ball plastic BGA packages. All packages are specified for a case temperature (T ensure that the T ...
Page 48
... ADSP-21061/ADSP-21061L 225-BALL PBGA PIN CONFIGURATIONS Table 32. ADSP-21061L 225-Lead Metric PBGA (B-225-2) Pin Assignments Pin PBGA Pin Name Pin Number Name BMS A01 ADDR25 ADDR30 A02 ADDR26 DMAR2 A03 MS2 DT1 A04 ADDR29 RCLK1 A05 DMAR1 TCLK0 A06 TFS1 RCLK0 A07 CPA ...
Page 49
... Table 32. ADSP-21061L 225-Lead Metric PBGA (B-225-2) Pin Assignments (Continued) Pin PBGA Pin PBGA Name Pin Number Name Pin Number DATA41 C13 DATA26 F13 DATA38 C14 DATA28 F14 DATA36 C15 DATA27 F15 DATA42 DATA44 DATA47 BR3 BR2 DATA39 DATA43 DATA45 ...
Page 50
... ADSP-21061/ADSP-21061L 240-LEAD MQFP PIN CONFIGURATIONS Table 33. ADSP-21061 MQFP/ED (SP-240); ADSP-21061L MQFP (S-240) Pin Assignments Pin Name Pin No. Pin Name Pin No. TDI 1 ADDR20 41 TRST 2 ADDR21 GND 43 DD TDO 4 ADDR22 44 TIMEXP 5 ADDR23 45 EMU 6 ADDR24 46 ICSA FLAG3 8 GND 48 FLAG2 ...
Page 51
... Figure 39. 240-Lead Metric Quad Flat Package, Thermally Enhanced [MQFP/ED] (SP-240-2) 34.60 BSC SQ 29.50 REF 4.10 SQ 3.78 3.55 240 1 PIN 1 HEAT SLUG TOP VIEW (PINS DOWN VIEW A 0.27 MAX 0.50 0.17 MIN BSC LEAD PITCH Rev Page July 2007 ADSP-21061/ADSP-21061L 181 180 24.00 REF SQ 32.00 BSC SQ 121 120 3.92 45° (4 PLACES) ...
Page 52
... ADSP-21061/ADSP-21061L 0.75 0.60 0.45 SEATING PLANE 0.50 BSC 0.27 0.17 0.08 MAX COPLANARITY 0.50 0.25 2.70 MAX 34.85 34.60 SQ 34.35 4.10 32.00 BSC SQ MAX PIN 3.50 3.40 3.20 Figure 40. 240-Lead Metric Quad Flat Package, [MQFP] (S-240) 23.20 23.00 SQ 22.80 BALL A1 INDICATOR 18.00 20.10 BSC SQ 20.00 SQ TOP VIEW 19.90 1.27 BSC 0. PLACES DETAIL A 0.70 0.60 0.50 SEATING PLANE BALL DIAMETER Figure 41. 225-Ball Plastic Ball Grid Array [PBGA] (B-225-2) Rev ...
Page 53
... ADSP-21061LKS-160 0°C to 85°C 1 ADSP-21061LKSZ-160 0°C to 85°C ADSP-21061LAS-176 –40°C to +85°C 1 ADSP-21061LASZ-176 –40°C to +85°C ADSP-21061LKS-176 0°C to 85°C 1 ADSP-21061LKSZ-176 0°C to 85° RoHS Compliant Part. Ball Attach Type Solder Mask Opening Solder Mask Defined 0.63 mm diameter ...
Page 54
... ADSP-21061/ADSP-21061L Rev Page July 2007 ...
Page 55
... Rev Page July 2007 ADSP-21061/ADSP-21061L ...
Page 56
... ADSP-21061/ADSP-21061L ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00170-0-7/07(C) Rev Page July 2007 ...