adsp-21992 Analog Devices, Inc., adsp-21992 Datasheet - Page 4

• Manufacturer Part Number: adsp-21992
• Description: Mixed Signal Dsp Controller With Can
• Manufacturer: Analog Devices, Inc.

ADSP-21992
an algebraic syntax for ease of coding and readability. A com-
prehensive set of development tools supports program
development.
The block diagram
embedded SHARC core. It contains three independent compu-
tational units: the ALU, the multiplier/accumulator (MAC), and
the shifter. The computational units process 16-bit data from
the register file and have provisions to support multiprecision
computations. The ALU performs a standard set of arithmetic
and logic operations; division primitives are also supported. The
MAC performs single cycle multiply, multiply/add, and multi-
ply/subtract operations. The MAC has two 40-bit accumulators,
which help with overflow. The shifter performs logical and
arithmetic shifts, normalization, denormalization, and derive
exponent operations. The shifter can be used to efficiently
implement numeric format control, including multiword and
block floating-point representations.
Register usage rules influence placement of input and results
within the computational units. For most operations, the data
registers of the computational units act as a data register file,
permitting any input or result register to provide input to any
unit for a computation. For feedback operations, the computa-
tional units let the output (result) of any unit be input to any
unit on the next cycle. For conditional or multifunction instruc-
tions, there are restrictions on which data registers may provide
inputs or receive results from each computational unit. For
more information, see the ADSP-2199x DSP Instruction Set
Reference.
(Figure
REGISTER
4
DM ADDRESS BUS
MULT
DATA
DAG1
FILE
ADSP-219x DSP CORE
4
PX
16
2) shows the architecture of the
REGISTERS
REGISTERS
16
4
RESULT
INPUT
DAG2
4
16-BIT
24
PM ADDRESS BUS
16
PM DATA BUS
24
DM DATA BUS
DMA CONNECT
I/O DATA
SEQUENCER
SHIFTER
PROGRAM
BARREL
64
CACHE
24-BIT
24
16
16
Rev. A | Page 4 of 60 | August 2007
ALU
Figure 2. Block Diagram
DMA ADDRESS
DMA DATA
ADDRESS 24 BIT
ADDRESS
FOUR INDEPENDENT BLOCKS
ADDRESS
INTERNAL MEMORY
I/O ADDRESS
ADDRESS
24
(MEMORY-MAPPED)
24
SYSTEM INTERRUPT
I/O REGISTERS
24 BIT
CONTROLLER
DMA CONTROLLER
CONTROL
BUFFERS
STATUS
A powerful program sequencer controls the flow of instruction
execution. The sequencer supports conditional jumps, subrou-
tine calls, and low interrupt overhead. With internal loop
counters and loop stacks, the ADSP-21992 executes looped code
with zero overhead; no explicit jump instructions are required
to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and pro-
gram memory). Each DAG maintains and updates four 16-bit
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is pre- or post-modified by the value of
one of four possible modify registers. A length value and base
address may be associated with each pointer to implement auto-
matic modulo addressing for circular buffers. Page registers in
the DAGs allow circular addressing within 64K word bound-
aries of each of the 256 memory pages, but these buffers may not
cross page boundaries. Secondary registers duplicate all the pri-
mary registers in the DAGs; switching between primary and
secondary registers provides a fast context switch.
Efficient data transfer in the core is achieved with the use of
internal buses:
16 BIT
16 BIT
• Program memory address (PMA) bus
• Program memory data (PMD) bus
• Data memory address (DMA) bus
• Data memory data (DMD) bus
• Direct memory access address bus
• Direct memory access data bus
18
DATA
DATA
DATA
DATA
PROGRAMMABLE
FLAGS (16)
COMMUNICATIONS
I/O PROCESSOR
PERIPHERALS
EXTERNAL PORT
EMBEDDED
CONTROL
PORTS
DATA BUS
ADDR BUS
AND
EMULATION
MUX
TEST AND
MUX
TIMERS
JTAG
(3)
16
20
3
6