adsp-21992 Analog Devices, Inc., adsp-21992 Datasheet - Page 50

• Manufacturer Part Number: adsp-21992
• Description: Mixed Signal Dsp Controller With Can
• Manufacturer: Analog Devices, Inc.

ADSP-21992
POWER DISSIPATION
Total power dissipation has two components, one due to inter-
nal circuitry and one due to the switching of external output
drivers. Internal power dissipation is dependent on the instruc-
tion execution sequence and the data operands involved.
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
and is calculated by the formula below.
The load capacitance includes the package capacitance (C
the processor). The switching frequency includes driving the
load high and then back low. Address and data pins can drive
high and low at a maximum rate of 1/(2t
can switch every cycle at a frequency of 1/t
at 1/(2t
estimate P
Table 27. P
Pin Type
Address
MSx
WR
Data
CLKOUT
• Number of output pins that switch during each cycle (O)
• The maximum frequency at which they can switch (f)
• Their load capacitance (C)
• Their voltage swing (V
• A system with one bank of external data memory—
• One 64K
asynchronous RAM (16-bit)
CK
), but selects can switch on each cycle. For example,
EXT
EXT
with the following assumptions:
Calculation Example
No. of Pins
15
1
1
16
1
16 RAM chip is used with a load of 10 pF
P
EXT
=
DD
O C
×
)
% Switching
50
0
50
×
V
DD
2
CK
×
CK
). The write strobe
f
. Select pins switch
Rev. A | Page 50 of 60 | August 2007
10 pF
10 pF
10 pF
10 pF
10 pF
IN
C
of
20 MHz
20 MHz
40 MHz
20 MHz
80 MHz
The P
drive as shown in
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation with
the following formula.
where:
P
P
Power
Note that the conditions causing a worst-case P
from those causing a worst-case P
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching
simultaneously.
EXT
INT
f
• Maximum peripheral speed CCLK = 80 MHz, HCLK =
• External data memory writes occur every other cycle, a rate
• The bus cycle time is 80 MHz (t
80 MHz
of 1/(4t
is I
is from
EXT
Dissipation.
DDINT
equation is calculated for each class of pins that can
HCLK
Table
), with 50% of the pins switching
2.5 V, using the calculation I
Table
27.
10.9 V
10.9 V
10.9 V
10.9 V
10.9 V
P
TOTAL
V
27.
DD
2
=
P
EXT
INT
+
HCLK
. Maximum P
= P
= 0.04687 W
= 0.01635 W
= 0.0 W
= 0.00436 W
= 0.01744 W
= 0.00872 W
P
INT
EXT
= 12.5 ns)
DDINT
EXT
INT
are different
listed in
cannot