adsp-2195mkca-160x Analog Devices, Inc., adsp-2195mkca-160x Datasheet - Page 18

• Manufacturer Part Number: adsp-2195mkca-160x
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

ADSP-2195
JTAG Emulator Pod Connector
Figure 9
at the 14-pin target end.
area for a target board header. The keep-out area allows the
pod connector to properly seat onto the target board header.
This board area should contain no components (chips,
resistors, capacitors, etc.). The dimensions are referenced
to the center of the 0.25" square post pin.
Figure 9. JTAG Pod Connector Dimensions
Figure 10. JTAG Pod Connector Keep-Out Area
Table 7. Pin Descriptions
18
Pin
A21–0
D7–0
D15
D14
D13
D12
/PF15
/SPI1SEL7
/PF14
/SPI0SEL7
/PF12
/SPI1SEL6
/PF12
/SPI0SEL6
details the dimensions of the JTAG pod connector
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
Type
O/T
I/O/T
I/O/T
I/O
I
I/O/T
I/O
I
I/O/T
I/O
I
I/O/T
I/O
I
Figure 10
Function
External Port Address Bus
External Port Data Bus, least significant 8 bits
Data 15 (if 16-bit external bus)/Programmable Flags 15 (if 8-bit external bus)/SPI1 Slave
Select output 7 (if 8-bit external bus, when SPI1 enabled)
Data 14 (if 16-bit external bus)/Programmable Flags 14 (if 8-bit external bus)/SPI0 Slave
Select output 7 (if 8-bit external bus, when SPI0 enabled)
Data 13 (if 16-bit external bus)/Programmable Flags 13 (if 8-bit external bus)/SPI1 Slave
Select output 6 (if 8-bit external bus, when SPI1 enabled)
Data 12 (if 16-bit external bus)/Programmable Flags 12 (if 8-bit external bus)/SPI0 Slave
Select output 6 (if 8-bit external bus, when SPI0 enabled)
For current information contact Analog Devices at 800/262-5643
displays the keep-out
Design-for-Emulation Circuit Information
For details on target board design issues including: single
processor connections, multiprocessor scan chains, signal
buffering, signal termination, and emulator pod logic, see
the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website (www.ana-
log.com)—use site search on “EE-68”. This document is
updated regularly to keep pace with improvements to
emulator support.
Additional Information
This data sheet provides a general overview of the
ADSP-2195 architecture and functionality. For detailed
information on the ADSP-219x family core architecture
and instruction set, refer to the ADSP-219x/2191 DSP
Hardware Reference.
PIN DESCRIPTIONS
ADSP-2195 pin definitions are listed in
ADSP-2195 inputs are asynchronous and can be asserted
asynchronously to CLKIN (or to TCK for TRST).
Unused inputs should be tied or pulled to V
except for ADDR21–0, DATA15–0, PF7-0, and inputs that
have internal pull-up or pull-down resistors (TRST,
BMODE0, BMODE1, OPMODE, BYPASS, TCK, TMS,
TDI, and RESET)—these pins can be left floating. These
pins have a logic-level hold circuit that prevents input from
floating internally.
The following symbols appear in the Type column of
Table
Supply, and T = Three-State.
7: G = Ground, I = Input, O = Output, P = Power
September 2001
Table
DDEXT
7. All
or GND,
REV. PrA