adsp-21462w Analog Devices, Inc., adsp-21462w Datasheet - Page 9

• Manufacturer Part Number: adsp-21462w
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
UART, two for the SPI interface, two for the external port, two
for DTCP (or memory-to-memory data transfer when DTCP is
not used), two for the link port, two for the FFT/FIR/IIR accel-
erators, and up to 31 DMA channels for the media local bus
interface on the ADSP-21462W and ADSP-21465W.
Programs can be downloaded to the ADSP-21462W/ADSP-
21465W/ADSP-21467 using DMA transfers. Other DMA fea-
tures include interrupt generation upon completion of DMA
transfers, and DMA chaining for automatic linked DMA
transfers.
Delay Line DMA
The ADSP-21462W/ADSP-21465W/ADSP-21467 processor
provides delay line DMA functionality. This allows processor
reads and writes to external delay line buffers (and hence to
external memory) with limited core interaction.
Scatter/Gather DMA
The ADSP-21462W/ADSP-21465W/ADSP-21467 processor
provides scatter/gather DMA functionality.
This allows processor DMA reads/writes to/from non-contin-
geous memory blocks.
Digital Applications Interface (DAI)
The digital applications interface (DAI) provides the ability to
connect various peripherals to any of the DAI pins
(DAI_P20–1).
Programs make these connections using the signal routing unit
(SRU), shown in
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon-
nected under software control. This allows easy use of the DAI
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with noncon-
figurable signal paths.
The DAI also includes eight serial ports, four precision clock
generators (PCG), S/PDIF transceiver, four ASRCs, and an
input data port (IDP). The IDP provides an additional input
path to the SHARC core, configurable as either eight channels
of serial data, or a single 20-bit wide synchronous parallel data
acquisition port. Each data channel has its own DMA channel
that is independent from the processor’s serial ports.
Serial Ports
The ADSP-21462W/ADSP-21465W/ADSP-21467 features
eight synchronous serial ports that provide an inexpensive
interface to a wide variety of digital and mixed-signal peripheral
devices such as Analog Devices’ AD183x family of audio codecs,
ADCs, and DACs. The serial ports are made up of two data
lines, a clock, and frame sync. The data lines can be pro-
grammed to either transmit or receive and each data line has a
dedicated DMA channel.
Serial ports can support up to 16 transmit or 16 receive channels
of audio data when all eight SPORTs are enabled, or four full
duplex TDM streams of 128 channels per frame.
Figure
1.
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ADSP-21462W/ADSP-21465W/ADSP-21467
The serial ports operate at a maximum data rate of 56.25 Mbps.
Serial port data can be automatically transferred to and from
on-chip memory/external memory via dedicated DMA chan-
nels. Each of the serial ports can work in conjunction with
another serial port to provide TDM support. One SPORT pro-
vides two transmit signals while the other SPORT provides the
two receive signals. The frame sync and clock are shared.
Serial ports operate in five modes:
Left-justified sample pair mode is a mode where in each frame
sync cycle two samples of data are transmitted/received—one
sample on the high segment of the frame sync, the other on the
low segment of the frame sync. Programs have control over var-
ious attributes of this mode.
Each of the serial ports supports the left-justified sample pair
and I
monly used by audio codecs, ADCs, and DACs such as the
Analog Devices AD183x family), with two data pins, allowing
four left-justified sample pair or I
devices) per serial port, with a maximum of up to 32 I
nels. The serial ports permit little-endian or big-endian
transmission formats and word lengths selectable from 3 bits to
32 bits. For the left-justified sample pair and I
word lengths are selectable between 8 bits and 32 bits. Serial
ports offer selectable synchronization and transmit modes as
well as optional -law or A-law companding selection on a per
channel basis. Serial port clocks and frame syncs can be inter-
nally or externally generated.
The serial ports also contain frame sync error detection logic
where the serial ports detect frame syncs that arrive early (for
example frame syncs that arrive while the transmission/recep-
tion of the previous word is occurring). All the serial ports also
share one dedicated error interrupt.
S/PDIF-Compatible Digital Audio Receiver/Transmitter
and Synchronous/Asynchronous Sample Rate Converter
The S/PDIF receiver/transmitter has no separate DMA chan-
nels. It receives audio data in serial format and converts it into a
biphase encoded signal. The serial data input to the
receiver/transmitter can be formatted as left justified, I
right justified with word widths of 16, 18, 20, or 24 bits.
The serial data, clock, and frame sync inputs to the S/PDIF
receiver/transmitter are routed through the signal routing unit
(SRU). They can come from a variety of sources such as the
SPORTs, external pins, the precision clock generators (PCGs),
and are controlled by the SRU control registers.
The sample rate converter (ASRC) contains four ASRC blocks
and is the same core as that used in the AD1896 192 kHz stereo
asynchronous sample rate converter and provides up to 128 dB
SNR. The ASRC block is used to perform synchronous or asyn-
• Standard DSP serial mode
• Multichannel (TDM) mode
• I
• Packed I
• Left-justified sample pair mode
2
2
S protocols (I
S mode
2
S mode
2
S is an industry-standard interface com-
2
S channels (using two stereo
2
S modes, data-
2
S chan-
2
S or