adsp-21462 Analog Devices, Inc., adsp-21462 Datasheet - Page 14

• Manufacturer Part Number: adsp-21462
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469
Table 7. Pin List (Continued)
Name
DDR2_BA
DDR2_CAS
DDR2_CKE
DDR2_CS
DDR2_DATA
DDR2_DM
DDR2_DQS
DDR2_DQS
DDR2_RAS
DDR2_WE
DDR2_CLK0,
DDR2_CLK0,
DDR2_CLK1,
DDR2_CLK1
DDR2_ODT
AMI_MS
FLAG[0]/IRQ0
FLAG[1]/IRQ1
FLAG[2]/IRQ2/
AMI_MS2
FLAG[3]/TIMEX P/
AMI_MS3
0–1
3-0
2-0
1-0
1-0
1-0
15-0
Type
O/T
O/T
O/T
O/T
I/O/T
O/T
I/O/T (Differential)
O/T
O/T
O/T (Differential)
O/T
O/T
I/O
I/O
I/O
I/O
LVTTL





SSTL1
8











Rev. PrC | Page 14 of 62 | January 2009
State
During
and After
Reset
High-Z/
Driven low
High-Z/
Driven
high
High-Z/
Driven low
High-Z/
Driven
high
High-Z
High-Z/
Driven
high
High-Z
High-Z/
Driven
high
High-Z/
Driven
high
High-Z/
driven low
High-Z/
Driven low
High-Z
High-Z
High-Z
High-Z
High-Z
Description
DDR2 Bank Address Input. Define which bank an ACTIVATE,
READ, WRITE, or PRECHARGE command is being applied. BA2–0
define which mode register including MR, EMR, EMR(2), and
EMR(3) is loaded during the LOAD MODE command.
DDR2 Column Address Strobe. Connect to DDR2_CAS pin, in
conjunction with other DDR2 command pins, defines the operation for
the DDR2 to perform.
DDR2 Clock Enable Output to DDR2. Active high signal. Connect to
DDR2 CKE signal.
DDR2 Chip Select. All commands are masked when DDR2_CS
driven high. DDR2_CS
DDR2_CS
DDR2 Data In/Out. Connect to corresponding DDR2_DATA pins.
DDR2 Input Data Mask. Mask for the DDR2 write data if driven high.
Sampled on both edges of DDR2_DQS at DDR2 side. DM0 corresponds
to DDR2_DATA 7–0 and DM1 corresponds to DDR2_DATA 15–8.
Data Strobe. Output with Write Data. Input with Read Data. DQS0
corresponds to DDR2_DATA 7–0 and DQS1 corresponds to DDR2_DATA
15–8.
DDR2 Row Address Strobe. Connect to DDR2_RAS pin, in conjunction
with other DDR2 command pins, defines the operation for the DDR2 to
perform.
DDR2 Write Enable. Connect to DDR2_WE pin, in conjunction with
other DDR2 command pins, defines the operation for the DDR2 to
perform
DDR2 Clock. Free running, minimum frequency not guaranteed during
reset.
DDR2 On Die Termination. ODT pin when driven high (along with
other requirements) enables the DDR2 termination resistances.
Memory Select Lines 0–1. These lines are asserted (low) as chip selects
for the corresponding banks of external memory on the AMI interface.
The MS
same time as the other address lines. When no external memory access
is occurring the MS
a conditional memory access instruction is executed, whether or not
the condition is true.
The MS1 pin can be used in EPORT/FLASH boot mode. For more infor-
mation, see the ADSP-2146x SHARC Processor Hardware Reference.
FLAG0/Interrupt Request0.
FLAG1/Interrupt Request1.
FLAG2/Interrupt Request2/Async Memory Select2.
FLAG3/Timer Expired/Async Memory Select3.
1-0
3-0
lines are decoded memory address lines that change at the
lines select the corresponding bank.
1-0
3-0
lines are inactive; they are active however when
Preliminary Technical Data
are decoded emory address lines. Each
3-0
is