adsp-21267skstz Analog Devices, Inc., adsp-21267skstz Datasheet - Page 36

• Manufacturer Part Number: adsp-21267skstz
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21267
OUTPUT DRIVE CURRENTS
Figure 28
ers of the ADSP-21267. The curves represent the current drive
capability of the output drivers as a function of output voltage.
TEST CONDITIONS
The ac signal specifications (timing parameters) appear
on page 18
disable time, output enable time, and capacitive loading.
Timing is measured on signals when they cross the 1.5 V level as
described in
are measured between the point that the first signal reaches
1.5 V and the point that the second signal reaches 1.5 V.
OUTPUT
-20
-40
-10
-30
Figure 29. Equivalent Device Loading for AC Measurements
20
40
30
10
OUTPUT 1.5V
Figure 30. Voltage Reference Levels for AC Measurements
PIN
0
TO
INPUT
0
shows typical I-V characteristics for the output driv-
OR
through
Figure 30 on page
V OL TBD
0.5
Figure 28. ADSP-21267 Typical Drive
Table 30 on page
SWEEP (V DDEXT ) VOLTAGE - V
1
(Includes All Fixtures)
1.5
30pF
36. All delays (in nanoseconds)
PRELIMINARY TECHNICAL DATA
V OH TBD
2
35. These include output
50
2.5
Rev. PrA | Page 36 of 44 | January 2004
3
1.5V
1.5V
Table 9
3.5
CAPACITIVE LOADING
Output delays and holds are based on standard capacitive loads:
12 pF on all pins (see
how output delays and holds vary with load capacitance (Note
that this graph or derating does not apply to output disable
delays. The graphs of
not be linear outside the ranges shown for Typical Output Delay
vs. Load Capacitance and Typical Output Rise Time (20%-80%,
V=Min) vs. Load Capacitance.
10.0
12.0
8.0
6.0
4.0
2.0
12
10
8
6
4
2
0
0
0
0
Figure 32. Typical Output Rise/Fall Time
Figure 31. Typical Output Rise Time
20
20
Figure
Figure
(20%-80%, V
(20%-80%, V
LOAD CAPACITANCE - PF
LOAD CAPACITANCE - pF
40
40
29).
31,
TBD
TBD
Figure 32
DDEXT
DDEXT
Figure 32
60
60
= Max)
= Min)
and
80
shows graphically
80
Figure 33
100
100
may
120
120