adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 47

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

DDR1 SDRAM Write Cycle Timing
Table 29. DDR1 SDRAM Write Cycle Timing, V
Parameter
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CK
CH
CL
DQSS
DS
DH
DSS
DSH
DQSH
DQSL
WPRE
WPST
AS
AH
DOPW
OPW
Clock Period
Clock High Pulse Width
Clock Low Pulse Width
Write CMD to First DQS
DQ/DQM Setup to DQS
DQ/DQM Hold to DQS
DQS Falling to CK Rising (DQS Setup)
DQS Falling to CK Rising (DQS Hold)
DQS High Pulse Width
DQS Low Pulse Width
DQS Write Preamble
DQS Write Postamble
Address and Control Output SETUP Time Relative to CK
Address and Control Output HOLD Time Relative to CK
DQ and DM Output Pulse Width (for Each)
Address and Control Output Pulse Width
DQ/DM
ADDR
DQS
CTL
CK
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
t AS
t OPW
t AH
t DQSS
t CK
Figure 17. DDR1 SDRAM Controller Write AC Timing
t WPRE
Rev. A | Page 47 of 88 | October 2008
DDDDR
Nominal 2.6V
t DS
t DOPW
t DH
t CH
t DSH
t CL
t DSS
t DQSL
t DQSH
Min
7.50
0.45
0.45
0.75
0.90
0.90
0.20
0.20
0.35
0.35
0.25
0.40
1.00
1.00
1.75
2.20
t WPST
Max
0.55
0.55
1.25
0.60
Unit
ns
t
t
t
ns
ns
t
t
t
t
t
t
ns
ns
ns
ns
CK
CK
CK
CK
CK
CK
CK
CK
CK