adsp2185 Analog Devices, Inc., adsp2185 Datasheet - Page 11

• Manufacturer Part Number: adsp2185
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

REV. 0
BIASED ROUNDING
A mode is available on the ADSP-2185 to allow biased round-
ing in addition to the normal unbiased rounding. When the
BIASRND bit is set to 0, the normal unbiased rounding opera-
tions occur. When the BIASRND bit is set to 1, biased round-
ing occurs instead of the normal unbiased rounding. When
operating in biased rounding mode all rounding operations with
MR0 set to 0x8000 will round up, rather than only rounding up
odd MR1 values.
MR Value
Before RND
00-0000-8000
00-0001-8000
00-0000-8001
00-0001-8001
00-0000-7FFF
00-0001-7FFF
This mode only has an effect when the MR0 register contains
0x8000; all other rounding operations work normally. This
mode allows more efficient implementation of bit-specified
algorithms that use biased rounding, for example the GSM
speech compression routines. Unbiased rounding is preferred
for most algorithms.
Note: BIASRND bit is Bit 12 of the SPORT0 Autobuffer Con-
trol register.
Instruction Set Description
The ADSP-2185 assembly language instruction set has an alge-
braic syntax that was designed for ease of coding and readabil-
ity. The assembly language, which takes full advantage of the
processor’s unique architecture, offers the following benefits:
• The algebraic syntax eliminates the need to remember cryptic
• Every instruction assembles into a single, 24-bit word that
• The syntax is a superset ADSP-2100 Family assembly lan-
• Sixteen condition codes are available. For conditional jump,
• Multifunction instructions allow parallel execution of an
For example:
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.
can execute in a single instruction cycle.
guage and is completely source and object code compatible
with other family members. Programs may need to be relo-
cated to use on-chip memory and conform to the ADSP-
2185’s interrupt vector and reset vector map.
call, return or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.
Biased
RND Result
00-0001-8000
00-0002-8000
00-0001-8001
00-0002-8001
00-0000-7FFF
00-0001-7FFF
Table VII.
Unbiased
RND Result
00-0000-8000
00-0002-8000
00-0001-8001
00-0002-8001
00-0000-7FFF
00-0001-7FFF
–11–
I/O Space Instructions
The instructions used to access the ADSP-2185’s I/O memory
space are as follows:
Syntax: IO(addr) = dreg
where addr is an address value between 0 and 2047 and dreg is
any of the 16 data registers.
Examples: IO(23) = AR0;
Description: The I/O space read and write instructions move
DESIGNING AN EZ-ICE
The ADSP-2185 has on-chip emulation support and an
ICE-Port™*, a special set of pins that interface to the EZ-ICE
These features allow in-circuit emulation without replacing the
target system processor by using only a 14-pin connection from
the target system to the EZ-ICE
14-pin connector to accept the EZ-ICE
14-pin plug. See the ADSP-2100 Family EZ-Tools data sheet for
complete information on ICE products.
The ICE-Port™* interface consists of the following ADSP-2185
pins:
EBR
EBG
ERESET
EMS
EINT
ECLK
ELIN
ELOUT
EE
These ADSP-2185 pins must be connected only to the EZ-ICE
connector in the target system. These pins have no function
except during emulation, and do not require pull-up or pull-down
resistors. The traces for these signals between the ADSP-2185
and the connector must be kept as short as possible, no longer
than three inches.
The following pins are also used by the EZ-ICE
BR
BG
RESET
GND
The EZ-ICE
control of the ADSP-2185 in the target system. This causes the
processor to use its ERESET, EBR and EBG pins instead of the
RESET, BR and BG pins. The BG output is three-stated.
These signals do not need to be jumper-isolated in your system.
The EZ-ICE
and a 14-pin female plug. The female plug is plugged onto the
14-pin connector (a pin strip header) on the target board.
dreg = IO(addr);
AR1 = IO(17);
®
®
* uses the EE (emulator enable) signal to take
* connects to your target system via a ribbon cable
data between the data registers and the I/O
memory space.
®
*-COMPATIBLE SYSTEM
®
*. Target systems must have a
®
*’s in-circuit probe, a
ADSP-2185
®
*:
®
*.
®
*