adsp2185 Analog Devices, Inc., adsp2185 Datasheet - Page 19

• Manufacturer Part Number: adsp2185
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

Parameter
Bus Request/Grant
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
t
t
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS
1
2
REV. 0
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
BH
BS
SD
SDB
SE
SEC
SDBH
SEH
the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.
BR Hold after CLKOUT High
BR Setup before CLKOUT Low
CLKOUT High to xMS, RD, WR Disable
xMS, RD, WR Disable to BG Low
BG High to xMS, RD, WR Enable
xMS, RD, WR Enable to CLKOUT Hig
xMS, RD, WR Disable to BGH Low
BGH High to xMS, RD, WR Enable
CLKOUT
PMS, DMS
BMS, RD
CLKOUT
BGH
BR
WR
BG
Figure 16. Bus Request–Bus Grant
t
SD
t
1
BH
1
t
BS
t
t
SDBH
SDB
2
2
–19–
Min
0.25 t
0.25 t
0
0
0.25 t
0
0
CK
CK
CK
– 7
+ 2
+ 17
t
t
SEH
SE
t
SEC
Max
0.25 t
CK
+ 10
ADSP-2185
Unit
ns
ns
ns
ns
ns
ns
ns
ns