cy8c5246pvi-092 Cypress Semiconductor Corporation., cy8c5246pvi-092 Datasheet

cy8c5246pvi-092

Manufacturer Part Number

cy8c5246pvi-092

Description

Programmable System-on-chip Psoc

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY8C5246PVI-092.pdf (85 pages)

Current page: 1 of 85
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General Description

With its unique array of configurable blocks, PSoC

peripheral functions in a single chip. The CY8C52 family offers a modern method of signal acquisition, signal processing, and control

with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to

ultrasonic signals. The CY8C52 family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The

CY8C52 family is also a high performance configurable digital system with some part numbers including interfaces such as USB,

multi-master I

routing to all I/O pins, and a high performance 32-bit ARM

level designs using a rich library of prebuilt components and boolean primitives using PSoC

design entry tool. The CY8C52 family provides unparalleled opportunities for analog and digital bill of materials integration while easily

accommodating last minute design changes through simple firmware updates.

Features

Cypress Semiconductor Corporation

Document Number: 001-55034 Rev. *A

Note

1. This feature on select devices only. See

32-bit ARM Cortex-M3 CPU core

Low voltage, ultra low power

Versatile I/O system

Digital peripherals

DC to 40 MHz operation

Flash program memory, up to 256 KB, 100,000 write cycles,

20 year retention, multiple security features

Up to 64 KB SRAM memory

2 KB EEPROM memory, 1 million cycles, 20 years retention

24 channel DMA with multilayer AHB bus access

• Programmable chained descriptors and priorities

• High bandwidth 32-bit transfer support

Wide operating voltage range: 0.5V to 5.5V

High efficiency boost regulator from 0.5V input to 1.8V to 5.0V

output

2 mA at 6 MHz

Low power modes including:

• 300 nA hibernate mode with RAM retention and LVD

• 2 µA sleep mode with real time clock and low voltage reset

28 to 72 I/O (62 GPIO, 8 SIO, 2 USBIO

Any GPIO to any digital or analog peripheral routability

LCD direct drive from any GPIO, up to 46x16 segments

1.2V to 5.5V I/O interface voltages, up to 4 domains

Maskable, independent IRQ on any pin or port

Schmitt trigger TTL inputs

All GPIO configurable as open drain high/low, pull up/down,

High-Z, or strong output

Configurable GPIO pin state at power on reset (POR)

25 mA sink on SIO

20 to 24 programmable PLD based Universal Digital Blocks

Full CAN 2.0b 16 RX, 8 TX buffers

Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator

Four 16-bit configurable timer, counter, and PWM blocks

Library of standard peripherals

• 8, 16, 24, and 32-bit timers, counters, and PWMs

C, and CAN. In addition to communication interfaces, the CY8C52 family has an easy to configure logic array, flexible

Ordering Information

[1]

•

)

PRELIMINARY

198 Champion Court

on page 79 for details.

Programmable System-on-Chip (PSoC

5 is a true system level solution providing MCU, memory, analog, and digital

[1]

Cortex™-M3 microprocessor core. Designers can easily create system

[1]

Analog peripherals (1.71V ≤ Vdda ≤ 5.5V)

Programming, debug, and trace

Precision, programmable clocking

Temperature and packaging

PSoC

• SPI, UART, I

• Many others available in catalog

Library of advanced peripherals

• Cyclic Redundancy Check (CRC)

• Pseudo Random Sequence (PRS) generator

• LIN Bus 2.0

• Quadrature decoder

1.024V±0.1% internal voltage reference across -40°C to

+85°C (14 ppm/°C)

SAR ADC, 12-bit at 1 Msps

Two comparators with 75 ns response time

JTAG (4 wire), Serial Wire Debug (SWD) (2 wire), Single Wire

Viewer (SWV), and TRACEPORT interfaces

Cortex-M3 Flash Patch and Breakpoint (FPB) block

Cortex-M3 Embedded Trace Macrocell™ (ETM™) gener-

ates an instruction trace stream.

Cortex-M3 Data Watchpoint and Trace (DWT) generates

data trace information

Cortex-M3 Instrumentation Trace Macrocell (ITM) can be

used for printf-style debugging

DWT, ETM, and ITM blocks communicate with off-chip debug

and trace systems via the SWV or TRACEPORT

Bootloader programming supportable through I

UART, USB, and other interfaces

1 to 72 MHz internal ±1% oscillator (over full temperature and

voltage range) with PLL

4 to 33 MHz crystal oscillator for crystal PPM accuracy

Internal PLL clock generation up to 40 MHz

32.768 kHz watch crystal oscillator

Low power internal oscillator at 1 kHz, 100 kHz

-40°C to +85°C degrees industrial temperature

48-pin SSOP, 68-pin QFN, and 100-pin TQFP package

options

•

San Jose

5: CY8C52 Family Data Sheet

CA 95134-1709

Creator™, a hierarchical schematic

[1]

Revised December 03, 2009

•

C, SPI,

408-943-2600

)

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