cy8c5246pvi-092 Cypress Semiconductor Corporation., cy8c5246pvi-092 Datasheet - Page 39

• Manufacturer Part Number: cy8c5246pvi-092
• Description: Programmable System-on-chip Psoc
• Manufacturer: Cypress Semiconductor Corporation.

Independent of the ALU operation, these functions are available:
7.2.2.8 Conditionals
Each datapath has two compares, with bit masking options.
Compare operands include the two accumulators and the two
data registers in a variety of configurations. Other conditions
include zero detect, all ones detect, and overflow. These condi-
tions are the primary datapath outputs, a selection of which can
be driven out to the UDB routing matrix. Conditional computation
can use the built in chaining to neighboring UDBs to operate on
wider data widths without the need to use routing resources.
7.2.2.9 Variable MSB
The most significant bit of an arithmetic and shift function can be
programmatically specified. This supports variable width CRC
and PRS functions, and in conjunction with ALU output masking,
can implement arbitrary width timers, counters and shift blocks.
7.2.2.10 Built in CRC/PRS
The datapath has built in support for single cycle Cyclic Redun-
dancy Check (CRC) computation and Pseudo Random
Sequence (PRS) generation of arbitrary width and arbitrary
polynomial. CRC/PRS functions longer than 8 bits may be imple-
mented in conjunction with PLD logic, or built in chaining may be
use to extend the function into neighboring UDBs.
7.2.2.11 Input/Output FIFOs
Each datapath contains two four-byte deep FIFOs, which can be
independently configured as an input buffer (system bus writes
to the FIFO, datapath internal reads the FIFO), or an output
buffer (datapath internal writes to the FIFO, the system bus reads
from the FIFO). The FIFOs generate status that are selectable
as datapath outputs and can therefore be driven to the routing,
to interact with sequencers, interrupts, or DMA.
Document Number: 001-55034 Rev. *A
Shift left
Shift right
Nibble swap
Bitwise OR mask
PRELIMINARY
Figure 7-9. Example FIFO Configurations
7.2.2.12 Chaining
The datapath can be configured to chain conditions and signals
such as carries and shift data with neighboring datapaths to
create higher precision arithmetic, shift, CRC/PRS functions.
7.2.2.13 Time Multiplexing
In applications that are over sampled, or do not need high clock
rates, the single ALU block in the datapath can be efficiently
shared with two sets of registers and condition generators. Carry
and shift out data from the ALU are registered and can be
selected as inputs in subsequent cycles. This provides support
for 16-bit functions in one (8-bit) datapath.
7.2.2.14 Datapath I/O
There are six inputs and six outputs that connect the datapath to
the routing matrix. Inputs from the routing provide the configu-
ration for the datapath operation to perform in each cycle, and
the serial data inputs. Inputs can be routed from other UDB
blocks, other device peripherals, device I/O pins, and so on. The
outputs to the routing can be selected from the generated condi-
tions, and the serial data outputs. Outputs can be routed to other
UDB blocks, device peripherals, interrupt and DMA controller,
I/O pins, and so on.
System Bus
System Bus
A0/A1/ALU
D0/D1
TX/RX
PSoC
F0
F1
®
5: CY8C52 Family Data Sheet
A0/A1/ALU
F0
Dual Capture
System Bus
A0/A1/ALU
F1
D0
F0
A0
System Bus
Dual Buffer
Page 39 of 85
D1
A1
F1
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